STC3500 datasheet(32/48 Pages) CONNOR-WINFIELD

32 / 48 page

Preliminary Data Sheet: TM060

Page 32 of 48

Rev: P06

Date: 11/22/04

Application Notes continued

Environment – The maximum device power dissipation is 2 W. Board layout and device location need to account for

adequate cooling.

All device input and output signal levels are 3.3V LVTTL (Except VC_PPECL and VC_NPECL, which are LVPECL).

External Component Selection – Following are the recommended external components to be used with the STC3500.

The device pins to which they connect are also shown. The main oscillator may be an OCXO or TCXO:

Component Selections

Table 8

Component

Vendor

Part Number/Description

Device Pins

OCXO (CT only)

Connor-Winfield

ASOF3S3 12.8 MHz

OCXO

AGOF3S3 12.8 MHz

OCXO (IT only)

Connor-Winfield

DSOF3S3 12.8 MHz

OCXO

BGOF3S3 12.8 MHz

TCXO (CT range only)

Connor-Winfield

T-501

TCXO

VCXO (CT range)

Connor-Winfield

VKB52B2 (- Sync_Clk frequency)

VCXO

VCXO (IT range)

Connor-Winfield

VKB62B2 (- Sync_Clk frequency)

VCXO

DAC

Linear Technology

LTC1655LCS8

DACclk, DACdin, DACld

EEPROM (Optional)

Atmel

AT24C64N-10SI-2.7

E2scl, E2sda, E2wp

The VCXO determines the Sync_Clk output frequency. Acceptable output frequencies are: 12.96 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz 51.84 MHz, 77.76 MHz, or 155.52 MHz. The device will operationally autodetect the output

frequency.

The EEPROM is optional, and is required to hold device configuration data if the application intends to operate in

hardware control mode only (No bus interface). If the bus interface is used, the application may provide the

configuration data pump, and no EEPROM is required. See Application Notes, Configuration Data section.

Reference Inputs – The application may supply up to 8 reference inputs, applied at input pins Ref1 - 8. They may each

be 8 kHz, 1.544 MHz, 2.048 MHz, 19.44 MHz, 38.88 MHz, or 77.76 MHz. The device auto-detects frequency in the

hardware control modes, and may auto-detect or have the frequency written to registers in register control mode, as

described in the control mode sections that follow.

References would typically (but need not be) connected in decreasing order of usage priority. For example if redundant

BITS clocks are available, they would typically be assigned to Ref1 and Ref2, with other transmission derived signals

following thereafter.

Master/slave operation – For some applications, reliability requirements may demand that the clock system to be

duplicated. The STC3500 device will support the master/slave duplicated configuration for such applications. To

facilitate it’s use, the device includes the necessary signal cross coupling and control functions. Redundancy for

reliability implies two major considerations: 1) Maintaining separate failure groups such that a failure in one group does

not affect it’s mate, and 2) Physical and logical partitioning for repair, such that a failed component can be replaced

while the mate remains in service, if so desired. System design needs to account for these appropriately for system

level goals to be met.

Master/Slave Configuration – A pair of devices are interconnected by cross-coupling their respective Sync_8K or

Sync_Clk outputs to the other device’s Xref input (See Figure 10). Note that 8 kHz frame phase alignment is

maintained across a master/slave pair of devices only if Sync_8K is used as the cross couple signal.

Additionally, the reference inputs for each device would typically be correspondingly the same, so that when a Master/

Slave switch occurs, synchronization would continue with the same reference. The references may be driven by the

same signal directly or via separate drivers, as the redundancy of that part of the system requires. Distribution path

lengths are not critical here, as a phase build-out will occur when a device switches from slave to master.

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