LTM8023 datasheet(6/20 Pages) LINER

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LTM8023

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PIN FUNCTIONS

VIN (Bank 1): The VIN pin supplies current to the LTM8023’s

internal regulator and to the internal power switch. This

pin must be locally bypassed with an external, low ESR

capacitor of at least 2.2μF.

VOUT (Bank 2): Power Output Pins. Apply the output ﬁlter

capacitor and the output load between these pins and

GND pins.

AUX (Pin F5): Low Current Voltage Source for BIAS. In

many designs, the BIAS pin is simply connected to VOUT.

The VAUX pin is internally connected to VOUT and is placed

adjacent to the BIAS pin to ease printed circuit board rout-

ing. Although this pin is internally connected to VOUT, do

NOT connect this pin to the load. If this pin is not tied to

BIAS, leave it ﬂoating.

BIAS (Pin G5): The BIAS pin connects to the internal power

bus. Connect to a power source greater than 2.8V. If the

output is greater than 2.8V, connect this pin there. If the

output voltage is less, connect this to a voltage source

between 2.8V and 16V. Also, make sure that BIAS + VIN

is less than 56V.

RUN/SS (Pin H5): Tie RUN/SS pin to ground to shut down

the LTM8023. Tie to 2.5V or more for normal operation.

If the shutdown feature is not used, tie this pin to the VIN

pin. RUN/SS also provides a soft-start function; see the

Applications Information section.

GND (Bank 3): Tie these GND pins to a local ground plane

below the LTM8023 and the circuit components. Return

the feedback divider (RADJ) to this net.

RT (Pin G7): The RT pin is used to program the switching

frequency of the LTM8023 by connecting a resistor from

this pin to ground. The Applications Information section of

the data sheet includes a table to determine the resistance

value based on the desired switching frequency. Minimize

capacitance at this pin.

SHARE (Pin F7): Tie this to the SHARE pin of another

LTM8023 when paralleling the outputs. Otherwise, do

not connect.

SYNC (Pin G6): This is the external clock synchronization

input. Ground this pin for low ripple Burst Mode operation

at low output loads. Tie to a stable voltage source greater

than 0.7V to disable Burst Mode operation.

Do not leave

this pin ﬂoating. Tie to a clock source for synchronization.

Clock edges should have rise and fall times faster than 1μs.

See synchronizing section in Applications Information.

PGOOD (Pin H6): The PGOOD pin is the open-collector

output of an internal comparator. PG remains low until the

ADJ pin is within 10% of the ﬁnal regulation voltage. PG

output is valid when VIN is above 3.6V and RUN/SS is high.

If this function is not used, leave this pin ﬂoating.

ADJ (Pin H7): The LTM8023 regulates its ADJ pin to 0.79V.

Connect the adjust resistor from this pin to ground. The

value of RADJ is given by the equation RADJ = 394.21/(VOUT

– 0.79), where RADJ is in k.

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