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LTC4440 Datasheet(PDF) 8 Page - Linear Technology

Part # LTC4440
Description  High Speed, High Voltage High Side Gate Driver
PDF  12 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC4440 Datasheet(HTML) 8 Page - Linear Technology

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LTC4440
4440f
Power Dissipation
To ensure proper operation and long-term reliability, the
LTC4440 must not operate beyond its maximum tempera-
ture rating. Package junction temperature can be calcu-
lated by:
TJ = TA + PD (θJA)
where:
TJ = Junction Temperature
TA = Ambient Temperature
PD = Power Dissipation
θJA = Junction-to-Ambient Thermal Resistance
Power dissipation consists of standby and switching
power losses:
PD = PSTDBY + PAC
where:
PSTDBY = Standby Power Losses
PAC = AC Switching Losses
The LTC4440 consumes very little current during standby.
The DC power loss at VCC = 12V and VBOOST–TS = 12V is
only (250µA + 110µA)(12V) = 4.32mW.
AC switching losses are made up of the output capacitive
load losses and the transition state losses. The capacitive
load losses are primarily due to the large AC currents
needed to charge and discharge the load capacitance
during switching. Load losses for the output driver driving
a pure capacitive load COUT would be:
Load Capacitive Power = (COUT)(f)(VBOOST–TS)2
The power MOSFET’s gate capacitance seen by the driver
output varies with its VGS voltage level during switching.
A power MOSFET’s capacitive load power dissipation can
be calculated using its gate charge, QG. The QG value
corresponding to the MOSFET’s VGS value (VCC in this
case) can be readily obtained from the manufacturer’s QG
vs VGS curves:
Load Capacitive Power (MOS) = (VBOOST–TS)(QG)(f)
Transition state power losses are due to both AC currents
required to charge and discharge the driver’s internal
nodal capacitances and cross-conduction currents in the
internal gates.
Undervoltage Lockout (UVLO)
The LTC4440 contains both low side and high side under-
voltage lockout detectors that monitor VCC and the
bootstrapped supply VBOOST–TS. When VCC falls below
6.2V, the internal buffer is disabled and the output pin OUT
is pulled down to TS. When VBOOST – TS falls below 6.9V,
OUT is pulled down to TS. When both supplies are under-
voltage, OUT is pulled low to TS and the chip enters a low
current mode, drawing approximately 25µA from VCC and
86µA from BOOST.
Bypassing and Grounding
The LTC4440 requires proper bypassing on the VCC and
VBOOST–TS supplies due to its high speed switching (nano-
seconds) and large AC currents (Amperes). Careless
component placement and PCB trace routing may cause
excessive ringing and under/overshoot.
To obtain the optimum performance from the LTC4440:
A. Mount the bypass capacitors as close as possible
between the VCC and GND pins and the BOOST and TS
pins. The leads should be shortened as much as pos-
sible to reduce lead inductance.
B. Use a low inductance, low impedance ground plane to
reduce any ground drop and stray capacitance. Remem-
ber that the LTC4440 switches >2A peak currents and
any significant ground drop will degrade signal integrity.
C. Plan the power/ground routing carefully. Know where
the large load switching current is coming from and
going to. Maintain separate ground return paths for the
input pin and the output power stage.
D. Keep the copper trace between the driver output pin and
the load short and wide.
E. When using the MS8E package, be sure to solder the
exposed pad on the back side of the LTC4440 package
to the board. Correctly soldered to a 2500mm2 double-
sided 1oz copper board, the LTC4440 has a thermal
resistance of approximately 40°C/W. Failure to make
good thermal contact between the exposed back side
and the copper board will result in thermal resistances
far greater than 40°C/W.
APPLICATIO S I FOR ATIO



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