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LTC6404

6404f

APPLICATIONS INFORMATION

The LTC6404’s input referred voltage noise contributes the

equivalent noise of a 140

Ω resistor. When the feedback

network is comprised of resistors whose values are less

than this, the LTC6404’s output noise is voltage noise

dominant (See Figure 10.):

≈+

⎛

⎝⎜

⎞

⎠⎟

•1

Feedback networks consisting of resistors with values

greater than about 200

Ω will result in output noise which

is resistor noise and ampliﬁer current noise dominant.

kT R

≈

() ++

⎛

⎝⎜

⎞

⎠⎟

••

• • • •

Lower resistor values (<100

Ω)alwaysresultinlowernoise

at the penalty of increased distortion due to increased load-

ing of the feedback network on the output. Higher resistor

values (but still less than 400

Ω) will result in higher output

noise, but improved distortion due to less loading on the

output. The optimal feedback resistance for the LTC6404

runs between 100

Ω to 400Ω. Higher resistances are not

recommended.

The differential ﬁltered outputs OUTF+ and OUTF– will have

a little higher spot noise than the unﬁltered outputs (due to

the two 50

Ω resistors which contribute 0.9nV/√Hz each),

but actually will provide superior Signal-to-Noise in noise

bandwidths exceeding 139MHz due to the noise-ﬁltering

function the ﬁlter provides.

Layout Considerations

Because the LTC6404 is a very high speed ampliﬁer, it is

sensitive to both stray capacitance and stray inductance.

Three pairs of power supply pins are provided to keep the

power supply inductance as low as possible to prevent

degradation of ampliﬁer 2nd Harmonic performance. It is

critical that close attention be paid to supply bypassing. For

single supply applications (Pins 3, 9 and 12 grounded) it

is recommended that 3 high quality 0.1μF surface mount

ceramic bypass capacitor be placed between pins 2 and

3, between pins 11and 12, and between pins10 and 9 with

direct short connections. Pins 3, 9 and 10 should be tied

directly to a low impedance ground plane with minimal

routing. For dual (split) power supplies, it is recommended

that at least two additional high quality, 0.1μF ceramic

capacitors are used to bypass pin V+ to ground and V– to

ground, again with minimal routing. For driving large loads

(<200

Ω),additionalbypasscapacitancemaybeneededfor

optimal performance. Keep in mind that small geometry

(e.g. 0603) surface mount ceramic capacitors have a much

higher self resonant frequency than do leaded capacitors,

and perform best in high speed applications.

Any stray parasitic capacitances to ground at the sum-

ming junctions IN+, and IN– should be kept to an absolute

minimum even if it means stripping back the ground plane

away from any trace attached to this node. This becomes

especially true when the feedback resistor network uses

resistor values >400

Ω in circuits with RF = RI. Excessive

peaking in the frequency response can be mitigated by add-

ing small amounts of feedback capacitance (0.5pF to 2pF)

around RF. Always keep in mind the differential nature of

the LTC6404, and that it is critical that the load impedances

seen by both outputs (stray or intended) should be as bal-

anced and symmetric as possible. This will help preserve

the natural balance of the LTC6404, which minimizes the

generation of even order harmonics, and preserves the

rejection of common mode signals and noise.

It is highly recommended that the VOCM pin be either hard

tied to a low impedance ground plane (in split supply

applications), or bypassed to ground with a high quality

ceramic capacitor whose value exceeds 0.01μF. This will

help stabilize the common mode feedback loop as well as

prevent thermal noise from the internal voltage divider and

Figure 10. LTC6404-1 Output Spot Noise vs Spot Noise

Contributed by Feedback Network Alone

RF = RI (Ω)

0.1

100

10k

6404 F10

FEEDBACK RESISTOR

NETWORK NOISE ALONE

TOTAL (AMPLIFIER AND

FEEDBACK NETWORK)

OUTPUT NOISE

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