LTM4612 datasheet(7/24 Pages) LINER

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LTM4612

4612f

PIN FUNCTIONS

VIN (Bank 1): Power Input Pins. Apply input voltage be-

tween these pins and PGND pins. Recommend placing

input decoupling capacitance directly between VIN pins

and PGND pins.

PGND (Bank 2): Power Ground Pins for Both Input and

Output Returns.

VOUT (Bank 3): Power Output Pins. Apply output load

between these pins and PGND pins. Recommend placing

output decoupling capacitance directly between these

pins and GND pins (see the LTM4612 Pin Conﬁguration

below).

VD (Pins B7, C7): Top FET Drain Pins. Add more capa-

citors between VD and ground to handle the input RMS

current and reduce the input ripple further.

DRVCC (Pins C10, E11, E12): These pins normally con-

nect to INTVCC for powering the internal MOSFET drivers.

They can be biased up to 6V from an external supply with

about 50mA capability. This improves efﬁciency at the

higher input voltages by reducing power dissipation in

the module.

INTVCC (Pin A7): This pin is for additional decoupling of

the 5V internal regulator.

PLLIN (Pin A8): External Clock Synchronization Input to the

Phase Detector. This pin is internally terminated to SGND

with a 50k resistor. Apply a clock above 2V and below

INTVCC. See the Applications Information section.

FCB (Pin M12): Forced Continuous Input. Connect this pin

to SGND to force continuous synchronization operation at

low load, to INTVCC to enable discontinuous mode opera-

tion at low load or to a resistive divider from a secondary

output when using a secondary winding.

TRACK/SS (Pin A9): Output Voltage Tracking and Soft-Start

Pin. When the module is conﬁgured as a master output,

then a soft-start capacitor is placed on this pin to ground

to control the master ramp rate. A soft-start capacitor can

be used for soft-start turn-on as a standalone regulator.

Slave operation is performed by putting a resistor divider

from the master output to the ground, and connecting the

center point of the divider to this pin. See the Applications

Information section.

MPGM (Pins A12, B11): Programmable Margining Input.

A resistor from these pins to ground sets a current that is

equal to 1.18V/R. This current multiplied by 10k will equal

a value in millivolts that is a percentage of the 0.6V refer-

ence voltage. See the Applications Information section.

To parallel LTM4612s, each requires an individual MPGM

resistor. Do not tie MPGM pins together.

fSET (Pin B12): Frequency Set Internally to 850kHz at 12V

Output. An external resistor can be placed from this pin to

ground to increase frequency. This pin can be decoupled

with a 1000pF capacitor. See the Applications Information

section for frequency adjustment.

VFB (Pin F12): The Negative Input of the Error Ampliﬁer.

Internally, this pin is connected to VOUT with a 100k preci-

sion resistor. Different output voltages can be programmed

with an additional resistor between the VFB and SGND pins.

See the Applications Information section.

MARG0 (Pin C12): LSB Logic Input for the Margining

Function. Together with the MARG1 pin, the MARG0 pin

will determine if a margin high, margin low, or no margin

state is applied. The pin has an internal pull-down resistor

of 50k. See the Applications Information section.

MARG1 (Pins C11, D12): MSB Logic Input for the Margin-

ing Function. Together with the MARG0 pin, the MARG1 pin

will determine if a margin high, margin low, or no margin

state is applied. The pins have an internal pull-down resistor

of 50k. See the Applications Information section.

SGND (Pins D9, H12): Signal Ground Pins. These pins

connect to PGND at output capacitor point.

LTM4612 Pin Conﬁguration

(See Package Description for Pin Assignments)

MARG1

DRVCC

VFB

PGOOD

SGND

FCB

VIN

BANK 1

PGND

BANK 2

VOUT

BANK 3

fSET

MARG0

LGA PACKAGE

133-LEAD (15mm × 15mm × 2.8mm)

TOP VIEW

SGND

810 11

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