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LTC3835

3835fc

APPLICATIONS INFORMATION

a 5V output, or a 4% to 20% loss for a 3.3V output.

Efﬁciency varies as the inverse square of VOUT for the

same external components and output power level. The

combined effects of increasingly lower output voltages

and higher currents required by high performance digital

systems is not doubling but quadrupling the importance

of loss terms in the switching regulator system!

4. Transition losses apply only to the topside MOSFET, and

become signiﬁcant only when operating at high input

voltages (typically 15V or greater). Transition losses

can be estimated from:

Transition Loss = (1.7) VIN2 IO(MAX) CRSS f

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efﬁciency degradation in portable systems. It is

very important to include these “system” level losses

during the design phase. The internal battery and fuse

resistance losses can be minimized by making sure that

CIN has adequate charge storage and very low ESR at

the switching frequency. A 25W supply will typically

require a minimum of 20μF to 40μF of capacitance hav-

ing a maximum of 20mΩ to 50mΩ of ESR. Other losses

including Schottky conduction losses during dead-time

and inductor core losses generally account for less than

2% total additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, VOUT shifts by

an amount equal to

ΔILOAD (ESR), where ESR is the ef-

fective series resistance of COUT. ΔILOAD also begins to

charge or discharge COUT generating the feedback error

signal that forces the regulator to adapt to the current

change and return VOUT to its steady-state value. During

this recovery time VOUT can be monitored for excessive

overshoot or ringing, which would indicate a stability

problem. OPTI-LOOP compensation allows the transient

response to be optimized over a wide range of output

capacitance and ESR values. The availability of the ITH pin

not only allows optimization of control loop behavior but

also provides a DC coupled and AC ﬁltered closed loop

response test point. The DC step, rise time and settling

at this test point truly reﬂects the closed loop response.

Assuming a predominantly second order system, phase

margin and/or damping factor can be estimated using the

percentage of overshoot seen at this pin. The bandwidth

can also be estimated by examining the rise time at the

pin. The ITH external components shown in the Typical

Application circuit will provide an adequate starting point

for most applications.

The ITH series RC-CC ﬁlter sets the dominant pole-zero

loop compensation. The values can be modiﬁed slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the ﬁnal PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1μs to 10μs will

produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop. Placing a power MOSFET directly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This is

why it is better to look at the ITH pin signal which is in the

feedback loop and is the ﬁltered and compensated control

loop response. The gain of the loop will be increased

by increasing RC and the bandwidth of the loop will be

increased by decreasing CC. If RC is increased by the same

factor that CC is decreased, the zero frequency will be kept

the same, thereby keeping the phase shift the same in the

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