LTC4110 datasheet(45/52 Pages) LINER

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LTC4110

4110fa

Figure 19. SMBus Protection

CONNECTOR

TO BATTERY

TO SYSTEM

4110 F19

VDD

INPUT AND OUTPUT CAPACITORS

The LTC4110 uses a synchronous ﬂyback regulator to

provide high battery charging current. A chip ceramic

capacitor is recommended for both the input and output

capacitors because it provides low ESR and ESL and can

handle the high RMS ripple currents. However, some

Hi-Q capacitors may produce high transients due to self

resonance under some start-up conditions, such as con-

necting the charger input to a hot power source. For more

information, refer to Application Note 88.

For charge mode, the ripple current can be calculated as

follows:

RMSDCINCAP

CHG

BAT

DCIN

=•

•

and

RMSBATCAP

CHG

BAT

DCIN

=•

•

For calibration mode, the ripple current can be calculated

as follows:

RMSDCINCAP

CAL

BAT

DCIN

=• •

•

and

RMSBATCAP

CAL

BAT

DCIN

=•

•

EMI considerations usually make it desirable to minimize

ripple current in the battery leads, and beads or induc-

tors may be added to increase battery impedance at the

300kHz switching frequency. Switching ripple current splits

between the battery and the output capacitor depending

on the ESR of the output capacitor and the battery imped-

ance. If the ESR of the output capacitor is 0.1Ω and the

battery impedance is raised to 2v with a bead or induc-

tor, only 5% of the ripple current will ﬂow in the battery.

APPLICATIONS INFORMATION

Similar techniques may also be applied to minimize EMI

from the input leads.

Diodes

Schottky diodes should be placed in parallel with the drain

and source of the Flyback MOSFETs. This prevents body

diode turn-on and improves efﬁciency by eliminating loss

from reverse recovery in these diodes. It also reduces

conduction loss during the dead time of the MOSFETs.

PROTECTING SMBUS PINS

The SMBus inputs, SCL and SDA, are exposed to uncon-

trolled transient signals whenever a battery is connected

to the system. If the battery contains a static charge, the

SMBus inputs are subjected to transients that can cause

damage after repeated exposure. Also, if the battery’s posi-

tive terminal makes contact to the connector before the

negative terminal, the SMBus inputs can be forced below

ground with the full battery potential, causing a potential

for latch-up in any of the devices connected to the SMBus

inputs. Therefore, it is good design practice to protect the

SMBus inputs as shown in Figure 19.

START-UP DELAYS

When exiting shutdown mode, internal supplies must

ramp up and settle. 500μs-1ms should be adequate after

shutdown is exited or when power is quickly (<100μs)

ﬁrst applied to the IC. For slow power ramp-up (>1ms)

internal supplies will be in regulation after power input

reaches 4.5V. Until internal supplies settle, status outputs

may be invalid.

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