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LTC3527/LTC3527-1

35271f

35271 F01

VIN1

VIN

VIN2

VOUT1

GND

MODE SHDN1

SHDN2 FSEL

VOUT2

APPLICATIONS INFORMATION

Figure 1. Recommended Component Placement for a Dual-Layer Board

Mode threshold) by reducing the inductor ripple cur-

rent. Increasing the inductance above 10µH will increase

size while providing little improvement in output current

capability.

The minimum inductance value is given by:

f Ripple V

IN MIN

OUT MAX

IN MIN

()

(

)

()

•(

–

)

••

TMAX

()

Where:

Ripple = Allowable inductor current ripple (amps peak-

to-peak)

VIN(MIN) = Minimum input voltage

VOUT(MAX) = Maximum output voltage

f = Oscillator frequency (MHz)

The inductor current ripple is typically set for 20% to

40% of the maximum inductor current. High frequency

ferrite core inductor materials reduce frequency dependent

power losses compared to cheaper powdered iron types,

improving efﬁciency. The inductor should have low ESR

(series resistance of the windings) to reduce the I2R power

losses, and must be able to support the peak inductor

current without saturating. Molded chokes and some

chip inductors usually do not have enough core area to

support the peak inductor currents of 900mA (500mA)

seen on the LTC3527/LTC3527-1. To minimize radiated

noise, use shielded inductors. See Table 1 for suggested

components and suppliers.

Output and Input Capacitor Selection

Low ESR (equivalent series resistance) capacitors should

be used to minimize output voltage ripple. Multilayer

ceramic capacitors are an excellent choice as they have

extremely low ESR and are available in small footprints.

A 4.7µF to 10µF output capacitor is sufﬁcient for most

applications. Larger values up to 22µF may be used to

obtain lower output voltage ripple and improve transient

response. X5R and X7R dielectric materials are preferred

for their ability to maintain capacitance over wide voltage

and temperature ranges. Y5V types should not be used.

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