LTC4009 datasheet(23/28 Pages) LINER

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LTC4009

LTC4009-1/LTC4009-2

The LTC4009 uses an improved adaptive TGATE and

BGATE drive that is insensitive to MOSFET inertial delays,

td(ON/OFF), to avoid overlap conduction losses. Switching

characteristics from power MOSFET data sheets apply

only to a speciﬁc test ﬁxture, so there is no substitute for

bench evaluation of external FETs in the target application.

In general, MOSFETs with lower inertial delays will yield

higher efﬁciency.

Diode Selection

A Schottky diode in parallel with the bottom FET and/or

top FET in an LTC4009 application clamps SW during the

non-overlap times between conduction of the top and

bottom FET switches. This prevents the body diode of the

MOSFETs from forward biasing and storing charge, which

could reduce efﬁciency as much as 1%. One or both diodes

can be omitted if the efﬁciency loss can be tolerated. A 1A

Schottky is generally a good size for 3A chargers due to the

low duty cycle of the non-overlap times. Larger diodes can

actually result in additional efﬁciency (transition) losses

due to larger junction capacitance.

Loop Compensation and Soft-Start

The three separate PWM control loops of the LTC4009

can be compensated by a single set of components at-

tached between the ITH pin and GND. As shown in the

typical LTC4009 application, a 6.04k resistor in series

with a capacitor of at least 0.1μF provides adequate loop

compensation for the majority of applications.

The LTC4009 can be soft-started with the compensation

capacitor on the ITH pin. At start-up, ITH will quickly rise

to about 0.25V, then ramp up at a rate set by the com-

pensation capacitor and the 40μA ITH bias current. The

full programmed charge current will be reached when ITH

reaches approximately 2V. With a 0.1μF capacitor, the time

to reach full charge current is usually greater than 1.5ms.

This capacitor can be increased if longer start-up times

are required, but loop bandwidth and dynamic response

will be reduced.

INTVDD Regulator Output

Bypass the INTVDD regulator output to GND with a low

ESR X5R or X7R ceramic capacitor with a value of 0.47μF

or larger. The capacitor used to build the BOOST supply

(C2 in Figure 11) can serve as this bypass. Do not draw

more than 30mA from this regulator for the host system,

governed by IC power dissipation.

Calculating IC Power Dissipation

The user should ensure that the maximum rated junction

temperature is not exceeded under all operating conditions.

The thermal resistance of the LTC4009 package (

θJA) is

37°C/W, provided the Exposed Pad is in good thermal

contact with the PCB. The actual thermal resistance in

the application will depend on forced air cooling and other

heat sinking means, especially the amount of copper on

the PCB to which the LTC4009 is attached. The following

formula may be used to estimate the maximum average

power dissipation PD (in watts) of the LTC4009, which is

dependent upon the gate charge of the external MOSFETs.

This gate charge, which is a function of both gate and drain

voltage swings, is determined from speciﬁcations or graphs

in the manufacturer’s data sheet. For the equation below,

ﬁnd the gate charge for each transistor assuming 5V gate

swing and a drain voltage swing equal to the maximum

VCLP voltage. Maximum LTC4009 power dissipation under

normal operating conditions is then given by:

PD = DCIN(2.8mA + IDD + 665kHz(QTGATE + QBGATE))

– 5IDD

where:

IDD = Average external INTVDD load current, if any

QTGATE = Gate charge of external top FET in Coulombs

QBGATE = Gate charge of external bottom FET in

Coulombs

APPLICATIONS INFORMATION

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