CDC509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS576B – JULY 1996 – REVISED JANUARY 1998

4

POST OFFICE BOX 655303

recommended operating conditions (see Note 4)

MIN

MAX

UNIT

VCC

Supply voltage

3

3.6

V

VIH

High-level input voltage

2

V

VIL

Low-level input voltage

0.8

V

VI

Input voltage

0

VCC

V

IOH

High-level output current

–20

mA

IOL

Low-level output current

20

mA

TA

Operating free-air temperature

0

70

°C

NOTE 4: Unused inputs must be held high or low to prevent them from floating.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP†

MAX

UNIT

VIK

II = –18 mA

3 V

–1.2

V

VOH

IOH = –100 µA

MIN to MAX

VCC–0.2

V

VOH

IOH = –20 mA

3 V

2.4

V

VOL

IOL = 100 µA

MIN to MAX

0.2

V

VOL

IOL = 20 mA

3 V

0.55

V

II

VI = VCC or GND

3.6 V

±5

µA

ICC‡

VI = VCC or GND,

IO = 0, Outptus high or low

3.6 V

10

µA

∆ICC

One input at VCC – 0.6 V,

Other inputs at VCC or GND

3.3 V to 3.6 V

500

µA

Ci

VI = VCC or GND

3.3 V

4

pF

Co

VO = VCC or GND

3.3 V

6

pF

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

‡ For ICC of AVCC, see Figure 5.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature

MIN

MAX

UNIT

fclock

Clock frequency

25

125

MHz

Input clock duty cycle

40%

60%

Stabilization time§

1

ms

§ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a

fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,

and jitter parameters given in the switching characteristics table are not applicable.