CDC516

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS575A – JULY 1996 – REVISED JANUARY 1998

7

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

LOAD CIRCUIT

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

tpd

50% VCC

3 V

0 V

VOH

VOL

Input

0.4 V

2 V

tr

tf

0.4 V

2 V

Output

500

W

50% VCC

30 pF

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR

≤ 100 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns.

C. The outputs are measured one at a time with one transition per measurement.

50% VCC

Figure 1. Load Circuit and Voltage Waveforms