EPC4 datasheet(29/36 Pages) ALTERA

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Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

Figure 10. EPC2 JTAG Waveforms

Table 11 shows the timing parameters and values for configuration

devices.

Operating

Conditions

Tables 12 through 19 provide information on absolute maximum ratings,

recommended operating conditions, DC operating conditions, and

capacitance for configuration devices.

Table 11. JTAG Timing Parameters & Values

Symbol

Parameter

Min

Max

Unit

tJCP

TCK

clock period

100

tJCH

TCK

clock high time

tJCL

TCK

clock low time

tJPSU

JTAG port setup time

tJPH

JTAG port hold time

tJPCO

JTAG port clock to output

tJPZX

JTAG port high impedance to valid output

tJPXZ

JTAG port valid output to high impedance

tJSSU

Capture register setup time

tJSH

Capture register hold time

tJSCO

Update register clock to output

tJSZX

Update register high-impedance to valid output

tJSXZ

Update register valid output to high impedance

TDO

TCK

tJPZX

tJPCO

tJPH

tJPXZ

tJCP

tJPSU

tJCL

tJCH

TDI

TMS

Signal

to Be

Captured

Signal

to Be

Driven

tJSZX

tJSSU

tJSH

tJSCO

tJSXZ

EPC4 Datasheet(PDF) 29 Page - Altera Corporation

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