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EPC4 Datasheet(PDF) 34 Page - Altera Corporation

Part # EPC4
Description  SRAM-Based LUT Devices
PDF  36 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EPC4 Datasheet(HTML) 34 Page - Altera Corporation

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Altera Corporation
Configuration Devices for SRAM-based LUT Devices Data Sheet
Revision
History
The information contained in the Configuration Devices for SRAM-Based
LUT Devices Data Sheet version 12.2 supersedes information published in
pervious versions. The following changes were made to the Configuration
Devices for SRAM-Based LUT Devices Data Sheet version 12.2:
Version 12.2
■
Corrected the APEX 20KE voltate in Table 2 to 1.8 V.
■
Updated Figure 5.
Version 12.1
■
Updated Table 2.
■
Updated notes to Figures 4, 5, and 6.
■
Added APEX 20KE device diagrams to Figures 4 and 6.
Table 24. FLEX 8000 Device Configuration Parameters Using EPC1, EPC1441, EPC1213, EPC1064 &
EPC1064V Devices
Symbol
Parameter
Conditions
EPC1064V
EPC1064
EPC1213
EPC1
EPC1441
Unit
Min Max Min Max Min Max
tOEZX
OE
high to DATA output enabled
75
50
50
ns
tCSZX
nCS
low to DATA output enabled
75
50
50
ns
tCSXZ
nCS
high to DATA output disabled
75
50
50
ns
tCSS
nCS
low setup time to first DCLK rising edge
150
100
50
ns
tCSH
nCS
low hold time after DCLK rising edge
0
0
0
ns
tDSU
Data setup time before rising edge on DCLK
75
50
50
ns
tDH
Data hold time after rising edge on DCLK
00
0
ns
tCO
DCLK
to DATA out delay
100
75
75
ns
tCK
Clock period
240
160
100
ns
fCK
Clock frequency
4
6
8
MHz
tCL
DCLK
low time
120
80
50
ns
tCH
DCLK
high time
120
80
50
ns
tXZ
OE
low or nCS high to DATA output disabled
75
50
50
ns
tOEW
OE
pulse width to guarantee counter reset
150
100
100
ns
tCASC
Last DCLK + 1 to nCASC low delay
90
60
50
ns
tCKXZ
Last DCLK + 1 to DATA tri-state delay
75
50
50
ns
tCEOUT
nCS
high to nCASC high delay
150
100
100
ns



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