MDC_HDAS-524/528.B01 Page 4 of 5

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HDAS-524, HDAS-528

12-Bit, 400kHz

, Complete

Data Acquisition System

Table 4. Output Coding

TECHNICAL NOTES

1. Rated performance requires using good high-frequency circuit board layout

techniques. The analog and digital ground pins are not connected to each

other internally. Avoid ground-related problems by connecting the analog,

signal and digital grounds to one point, the ground plane beneath the con-

verter. Due to the inductance and resistance of the power supply return paths,

return the analog and digital grounds separately to the power supplies. This

prevents contamination of the analog ground by noisy digital ground currents.

2. Double-level multiplexing allows expanding the multiplexer channel capacity

of the HDAS-528 from 8 single-ended channels to 128 single-ended chan-

nels or the HDAS-524 from 4 differential channels to 32 differential channels.

UNIPOLAR

INPUT RANGE

OUTPUT CODING

INPUT RANGE

BIPOLAR

SCALE

0 to +10V

MSB

LSB

MSB

LSB

±10V

SCALE

+FS – 1LSB

+9.9976V

1111 1111 1111

0000 0000 0000

+9.9951V

+FS – 1LSB

+7/8FS

+8.7500V

1110 0000 0000

0001 1111 1111

+7.5000V

+3/4FS

+3/4FS

+7.5000V

1100 0000 0000

0011 1111 1111

+5.0000V

+1/2FS

+1/2FS

+5.0000V

1000 0000 0000

0111 1111 1111

0.0000V

0

+1/4FS

+2.5000V

0100 0000 0000

1011 1111 1111

–5.0000V

–1/2FS

+1/8FS

+1.2500V

0010 0000 0000

1101 1111 1111

–7.5000V

–3/4FS

+1LSB

+0.0024V

0000 0000 0001

1111 1111 1110

–9.9951V

–FS + 1LSB

0

0.0000V

0000 0000 0000

1111 1111 1111

–10.0000V

–FS

STRAIGHT BINARY

COMP. BINARY

OFFSET BINARY

COMP. OFF. BINARY

Notes:

1. A START CONVERT pulse greater than

150ns will slow the throughput.

2. Retriggering START CONVERT before

EOC goes low will not start a new

conversion.

3. Times shown apply over the 0 to +70°C

operating temperature range.

20ns min.

35ns max.

100ns min.

850ns

1.8µs

N –1 Valid

30ns

30ns

40ns typical

START

CONVERT

OUTPUT

DATA

CA1

CA0

CH0 ADDRESSED

CH1 ADDRESSED

CH2 ADDRESSED

35ns

ENABLE

EOC

30ns

Disable N – 1

N – 1

N

40ns typical

N –1 Valid

N Valid

Enabled data

N Valid

Figure 3. HDAS-524/528 Timing Diagram

3. Obtain straight binary/offset binary output coding by tying COMP BIN (pin 9)

to +5V or leaving it open. The device has an internal pull-up resistor on this

pin. To obtain complementary binary or complementary offset binary output

coding, tie pin 9 to ground. The COMP BIN signal is compatible to CMOS/TTL

logic levels for those users desiring logic control of this function.

4. To enable the three-state outputs, connect ENABLE (pin 34) to a logic "0"

(low). To disable, connect pin 34 to a logic "1" (high).