UM0470 datasheet(33/37 Pages) STMICROELECTRONICS

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UM0470

Debug module (DM)

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4.12.10

DM control/status register 2 (DM_CSR2)

Address: 7F99h

Reset value: 0000 0000 (00h)

765

432

Reserved

SWBRK

SWBKF

STALL

Reserved

FLUSH

Bits 7:6

Reserved. Must be kept at 0

Bit 5

SWBKE Software breakpoint control bit (read/write)

This bit is used to enable/disable the software breakpoint capability with NOP

instruction

0: DM does not generate any event when NOP(SW BRK) instruction is fetched by

CPU

1: DM generates an event (CPU stalled in SWIM mode) when a software break

instruction is fetched by CPU.

Bit 4

SWBKF Software breakpoint status bit (read only)

This flag is set when the CPU executes the software break instruction.

0: No software break instruction detected.

1: Software break instruction detected. This bit is cleared when the STALL bit is

cleared.

Bit 3

STALL CPU stall control bit (R/W only in SWIM mode)

This bit is used to stall the CPU. This bit is kept cleared if the device is not in SWIM

mode.

This bit is set by WOTF command to generate an ABORT equivalent command

It is also set by an DM trap interrupt event.

This bit is cleared by WOTF command to re-start the CPU.

0: CPU runs normally

1: CPU is stalled

Bit: 2:1

Reserved. Must be kept at 0

Bit: 10

FLUSH Flush decode

This bit is set by software to flush the instruction decode phase after a PC

modification. It is cleared by hardware when the flush is completed.

0: Default status

1: Flush decode

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