SN65LVDT2

HIGH-SPEED DIFFERENTIAL LINE RECEIVER

SLLS374B – JULY 1999 – REVISED JANUARY 2000

8

POST OFFICE BOX 655303

APPLICATION INFORMATION

fail safe

One of the most common problems with differential signaling applications is how the system responds when

no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in

that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100

mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it

handles the open-input circuit situation, however.

Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be

when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver

feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the

output to a high-level regardless of the differential input voltage.

Rt = 100

Ω (Typ)

300 k

Ω

300 k

Ω

VCC

VIT ≈ 2.3 V

A

B

Y

Figure 8. Open-Circuit Fail Safe of the LVDS Receiver

It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential

input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as

long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that

could defeat the pullup currents from the receiver and the fail-safe feature.