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LTC2204 Datasheet(PDF) 6 Page - Linear Technology

Part # LTC2204
Description  16-Bit, 65Msps/40Msps
PDF  36 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC2204 Datasheet(HTML) 6 Page - Linear Technology

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LTC2205/LTC2204
6
22054fb
TIMING DIAGRAM
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND, with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 65MHz (LTC2205), 40MHz (LTC2204)
differential ENC+/ENC– = 2VP-P sine wave with 1.6V common mode,
input range = 2.25VP-P with differential drive (PGA = 0), unless otherwise
specified.
Note 5: Integral nonlinearity is defined as the deviation of a code from
a “best fit straight line” to the transfer curve. The deviation is measured
from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code flickers between 0000 0000 0000 0000 and 1111 1111 1111
1111 in 2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
The
l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
LTC2204
TYP
MAX
MIN
LTC2205
TYP
MAX
UNITS
fS
Sampling Frequency
l
1
40
1
65
MHz
tL
ENC Low Time
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
l
l
10.4
2.7
12.5
12.5
500
500
6.40
2.70
7.69
7.69
500
500
ns
ns
tH
ENC High Time
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
l
10.4
2.7
12.5
12.5
500
500
6.40
2.70
7.69
7.69
500
500
ns
ns
tAP
Sample-and-Hold
Aperture Delay
0.7
0.7
ns
tD
ENC to DATA Delay
(Note 7)
l
1.3
2.7
4.0
1.3
2.7
4.0
ns
tC
ENC to CLKOUT Delay
(Note 7)
l
1.3
2.7
4.0
1.3
2.7
4.0
ns
tSKEW
DATA to CLKOUT Skew
(tD – tC) (Note 7)
l
–0.6
0
0.6
–0.6
0
0.6
ns
tOE
DATA Access Time
Bus Relinquish Time
CL = 5pf (Note 7)
(Note 7)
l
l
5
5
15
15
5
5
15
15
ns
ns
Pipeline
Latency
7
7
Cycles
TIMING CHARACTERISTICS
tH
tD
tC
tL
N – 7
N – 6
N – 5
N – 4
N – 3
ANALOG
INPUT
ENC–
ENC+
CLKOUT –
CLKOUT+
D0-D15, OF
22054 TD01
tAP
N + 1
N + 2
N + 4
N + 3
N



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