THS10064 datasheet(18/41 Pages) TI

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THS10064

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

ADC control registers

control register 0 (see Table 8)

–

BIT 9

BIT 8

BIT 7

BIT 6

–

TEST1

TEST0

SCAN

DIFF1

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DIFF0

CHSEL1

CHSEL0

MODE

VREF

Table 9. Control Register 0 Bit Functions

BITS

RESET

VALUE

NAME

FUNCTION

VREF

Vref select:

Bit 0 = 0

→ The internal reference is selected

Bit 0 = 1

→ The external reference voltage is selected

MODE

Continuous conversion mode/single conversion mode

Bit 1 = 0

→ Continuous conversion mode is selected

An external clock signal is applied to the CONV_CLK input in this mode. With every falling edge of the

CONV_CLK signal a new converted value is written into the FIFO.

Bit 1 = 1

→ Single conversion mode is selected

In this mode, the CONV_CLK input functions as a CONVST input. A single conversion is initiated on the

THS10064 by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages of

the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the

selected channels is started. The signal DATA_AV (data available) becomes active when the trigger

condition is satisfied.

Power down.

Bit 2 = 0

→ The ADC is active

Bit 2 = 1

→ Power down

The reading and writing to and from the digital outputs is possible during power down. It is also possible to

read out the FIFO.

3, 4

0,0

CHSEL0,

CHSEL1

Channel select

Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 10.

5,6

1,0

DIFF0, DIFF1

Number of differential channels

Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 10.

SCAN

Autoscan enable

Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 10.

8,9

0,0

TEST0,

TEST1

Test input enable

Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This

feedback allows the check of all hardware connections and the ADC operation.

Refer to Table 11 for selection of the three different test voltages.

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