THS1206

12-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTERS

SLAS217D – MAY 1999 – REVISED APRIL 2000

27

POST OFFICE BOX 655303

timing and signal description of the THS1206 (continued)

read timing (using RD, RD-controlled)

Figure 15 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The

input RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last

external signal of CS0, CS1, and RD which becomes valid.

90%

90%

90%

10%

tw(RD)

tsu(CS)

th(CS)

ta

th

td(CSDAV)

CS0

CS1

WR

RD

D(0–11)

DATA_AV

10%

Figure 15. Read Timing Diagram Using RD (RD-controlled)

read timing parameter (RD-controlled)

PARAMETER

MIN

TYP

MAX

UNIT

tsu(CS)

Setup time, RD low to last CS valid

0

ns

ta

Access time, last CS valid to data valid

0

10

ns

td(CSDAV) Delay time, last CS valid to DATA_AV inactive

12

ns

th

Hold time, first CS invalid to data invalid

0

5

ns

th(CS)

Hold time, RD change to first CS invalid

5

ns

tw(RD)

Pulse duration, RD active

10

ns