TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

2

POST OFFICE BOX 655303

AVAILABLE OPTIONS

TA

PACKAGED DEVICES

TA

SOIC-28

TSSOP-28

0

°C to 70°C

TLV5580CDW

TLV5580CPW

–40

°C to 85°C

TLV5580IDW

TLV5580IPW

functional block diagram

SHA

DAC

ADC

+

–

ADC

Correction Logic

Output Buffers

22

2

2

2

D0(LSB)–D7(MSB)

2

2

SHA

SHA

SHA

SHA

SHA

The single-pipeline architecture uses 6 ADC/DAC stages and one final flash ADC. Each stage produces a

resolution of 2 bits. The correction logic generates its result using the 2-bit result from the first stage, 1 bit from

each of the 5 succeeding stages, and 1 bit from the final stage in order to arrive at an 8-bit result. The correction

logic guarantees no missing codes over the full operating temperature range.