TLV5590

2-BIT ANALOG-TO-DIGITAL CONVERTER

FOR FLEX

t PAGER CHIPSET

SLAS134B – NOVEMBER 1995 – REVISED NOVEMBER 1996

6

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

Value A

Value B

Based on Value A

Based on Value B

CLK

TRACKINH

(external)

TRACKINH

(internal)

Peak/Valley

Counter Value

EXTS0, EXTS1

Outputs

See Note A

NOTE A: Internally the device recognizes input conditions on the falling edge of the clock only.

Figure 1. Timing Diagram

CLK

CON1

CON2

TRACKINH

NOTES: A. Internally the device recognizes input conditions on the falling edge of the clock only.

B. On the next falling edge of the clock with the input conditions shown, the TLV5590 tracks signal in fast mode (peak DAC counter

counts down by 8 and up by 4) in time A.

C. On the next falling edge of the clock with the input conditions shown, the TLV5590 tracks signal in slow mode (peak DAC counter

counts up by 2 and down by 1 every 40 clock cycles) in time B.

D. On the next falling edge of the clock with the input conditions shown, the TLV5590 holds previous peak and valley levels in time

C. For the 2 bit ADC, when TRACKINH = 1, EXTS0 and EXTS1 outputs respond in real time to the condition of SIG and DC

OFFSET as long as the CLK signal is present.

See Note B

See Note C

See Note D

Time A

Time B

Time C

See Note A

Figure 2. Track and Lock Timing