TLV5590

2-BIT ANALOG-TO-DIGITAL CONVERTER

FOR FLEX

t PAGER CHIPSET

SLAS134B – NOVEMBER 1995 – REVISED NOVEMBER 1996

3

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

DESCRIPTION

AVDD

2

I

Analog supply voltage

BW

7

I

Digital bandwidth select. A high level on BW selects the 2-kHz filter cutoff and a low level selects the 1-kHz

filter cutoff.

CON1

8

I

Digital control 1 input. In conjunction with CON2, CON1 selects the fast acquisition mode, slow acquisition

mode, hold or standby.

CON2

9

I

Digital control 2 input. In conjunction with CON1, CON2 selects the fast acquisition mode, slow acquisition

mode, hold or standby.

CLK

14

I

Digital clock input. CLK input is a 50% duty cycle TTL-level clock input with nominal frequency of 38.4 kHz.

The CLK input is edge sensitive in all non-test modes. For all test modes, the CLK input is level sensitive.

DC OFFSET

4

I

Analog dc offset correction input. The dc component of the audio signal should be applied to DC OFFSET.

DVDD

1

I

Digital supply voltage

EXTS0

11

O

Digital output 0 of the ADC. Data bit 0 is the LSB.

EXTS1

10

O

Digital output 1 of the ADC. Data bit 1 is the MSB.

GND

6

Return terminal for the IC current.

SIG

3

I

Analog audio signal input. An appropriate RC low-pass filter (antialiasing filter) should be connected to SIG.

MID

5

O

Analog midpoint output. MID is a buffered output of AVDD/2.

TEST

13

I

Digital test input enable. TEST should be connected to ground in normal operation.

TRACKINH

12

I

Digital track inhibit logic input. A high level on TRACKINH disables the peak and valley detector counters, and

a low level enables the peak and valley detector counters. The counters continue to decay at the decay rate

while TRACKINH is a low level.