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TMS77C82 Datasheet(PDF) 28 Page - Texas Instruments |
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TMS77C82 Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 63 page ![]() TMS370CxCx 8-BIT MICROCONTROLLER SPNS040B – NOVEMBER 1995 – REVISED FEBRUARY 1997 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 serial communications interface 2 module (continued) Bit 5 PARITY ENABLE (SCI parity enable) This bit enables or disables the parity function. When parity is enabled during the address bit multiprocessor mode, the address bit is included in the parity calculation. 0 = Disables parity. No parity bit is generated during transmission or expected during reception. 1 = Enables parity Bit 6 EVEN/ODD PARITY (SCI parity enable) If the PARITY ENABLE bit is set, this bit selects odd or even parity (odd or even number of bits in both transmitted and received characters). 0 = Sets odd parity 1 = Sets even parity Bit 7 STOP BITS (SCI number of stop bits) This bit determines the number of stop bits transmitted. The receiver checks for one stop bit only. 0 = One stop bit 1 = Two stop bits SCI control register (SCICTL) The SCICTL register controls the RX/TX enable, TXWAKE and SLEEP functions, and the SCI software reset. Table 17. SCI Control Register (SCICTL) [Memory Address – 1051h] Bit # 7 65 43 21 0 P051 — — SCI SW RESET CLOCK ENABLE TXWAKE SLEEP TXENA RXENA RW – 0 RW – 0 RS – 0 RW – 0 RW – 0 RW – 0 R = read, W = write, S = set only, – n = value of the bit after the register is reset Bit 0 RXENA (SCI receive enable) When this bit is set, received characters are transferred into RXBUF, and the RXRDY flag is set. When cleared, this bit prevents received characters from being transferred into the receiver buffer (RXBUF), and no receiver interrupts are generated. However, the receiver shift register continues to assemble characters. As a result, if RXENA is set during the reception of a character, the complete character is transferred into RXBUF. 0 = Disables SCI receiver 1 = Enables SCI receiver Bit 1 TXENA (SCI transmit enable) Data transmission through the SCITXD pin occurs only when this bit is set. If this bit is reset, the transmission is not halted until all the data previously written to TXBUF has been sent. 0 = Disables SCI transmitter 1 = Enables SCI transmitter |
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