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TPS5103DB Datasheet(PDF) 27 Page - Texas Instruments |
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TPS5103DB Datasheet(HTML) 27 Page - Texas Instruments |
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27 / 37 page ![]() TPS5103 MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER SLVS240 – SEPTEMBER 1999 27 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION synchronization Some applications require switching clock synchronization. Two methods are used for synchronization: D Triangle wave synchronization TPS5103 Ct Rt 740 mV 740 mV D Square wave synchronization It can be seen that RT and CT are removed from the circuit. Therefore, two components are saved. This method is good for the synchronization between two controllers. If the controller needs to be synchronized with digital circuit such as DSP, usually the square-type clock signal is used. The configuration exhibited below is for this type of application: TPS5103 Ct Rt An external resistor is added into the circuit, but RT is still removed. CT is kept to be a part of RC circuit generating triangle waveform for the controller. Assuming the peak value of the square is known, the resistor and the capacitor can be adjusted to achieve the correct peak–to–peak value and the offset value. layout guidelines Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise pickup and generation and can cause a good design to perform with less than expected results. With a range of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult than most general PCB designs. The general design should proceed from the switching node to the output, then back to the driver section and, finally, place the low-level components. Below are several specific points to consider before layout of a TPS5103 design begins. D All sensitive analog components should be referenced to ANAGND. These include components connected to Vref5, Vref, INV, LH, and COMP . D Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect to the ground side of the bulk storage capacitors on VO, and drive ground will connect to the main ground plane close to the source of the low-side FET. |
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