TPS75201QPWPR datasheet(17/29 Pages) TI

17 / 29 page

TPS75201Q, TPS75215Q, TPS75218Q, TPS75225Q, TPS75233Q WITH RESET

TPS75401Q, TPS75415Q, TPS75418Q, TPS75425Q, TPS75433Q WITH POWER GOOD

FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS

SLVS242B – MARCH 2000 – REVISED JUNE 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following application

focuses mainly on the parasitic resistance ESR.

Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage.

LDO

VESR

RESR

RLOAD

–

Figure 22. LDO Output Stage With Parasitic Resistances ESR and ESL

In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across

the capacitor is the same as the output voltage (V(CO) = VO). This means no current is flowing into the CO

branch. If IO suddenly increases (transient condition), the following occurs:

D The LDO is not able to supply the sudden current need due to its response time (t1 in Figure 24). Therefore,

capacitor CO provides the current for the new load condition (dashed arrow). CO now acts like a battery with

an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at

RESR. This voltage is shown as VESR in Figure 23.

D When CO is conducting current to the load, initial voltage at the load will be VO = V(CO) – VESR. Due to the

discharge of CO, the output voltage VO will drop continuously until the response time t1 of the LDO is reached

and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it

reaches the regulated voltage. This period is shown as t2 in Figure 24.

The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels

of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.

From above, the following conclusions can be drawn:

D The higher the ESR, the larger the droop at the beginning of load transient.

D The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the

LDO response period.

TPS75201QPWPR Datasheet(PDF) 17 Page - Texas Instruments