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PCM1795DB Datasheet(PDF) 44 Page - Texas Instruments

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Part # PCM1795DB
Description  32-Bit, 192-kHz Sampling, Advanced Segment, Stereo Audio Digital-to-Analog Converter
PDF  58 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCM1795DB Datasheet(HTML) 44 Page - Texas Instruments

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Requirements for System Clock
t =1/(64
44.1kHz)
´
D1
DSDL,
DSDR
D0
D2
D3
D4
DBCK
DSDL,
DSDR
t
(BCH)
DBCK
t
(BCL)
t
(BCY)
1.4V
1.4V
t
(DS)
t
(DH)
DSD MODE CONFIGURATION AND FUNCTION CONTROLS
Configuration for the DSD Interface Mode
PCM1795
SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com
For operation in DSD mode, the bit clock (DBCK) is required on pin 7 of the PCM1795. The frequency of the bit
clock can be N times the sampling frequency. Generally, N is 64 in DSD applications.
The interface timing between the bit clock and DSDL and DSDR is required to meet the setup and hold time
specifications shown in Figure 60 and Table 13.
Figure 59. Normal Data Output Form From DSD Decoder
Figure 60. Timing for DSD Audio Interface
Table 13. Timing Characteristics for Figure 60
PARAMETER
MIN
MAX
UNIT
t(BCY)
DBCK pulse cycle time
85(1)
ns
t(BCH)
DBCK high-level time
30
ns
t(BCL)
DBCK low-level time
30
ns
t(DS)
DSDL, DSDR setup time
10
ns
t(DH)
DSDL, DSDR hold time
10
ns
(1)
2.8224 MHz × 4. (2.8224 MHz = 64 × 44.1 kHz. This value is specified as a sampling rate of DSD.
The DSD interface mode is selected by setting DSD = 1 (register 20, B5).
Table 14. DSD Mode Register Map
REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
0
1
0
0
0
0
X(1)
X
X
X
X
X
X
X
Register 17
R/W
0
0
1
0
0
0
1
X
X
X
X
X
X
X
X
Register 18
R/W
0
0
1
0
0
1
0
X
X
X
X
DMF1
DMF0
X
X
Register 19
R/W
0
0
1
0
0
1
1
REV
X
X
OPE
X
X
X
X
Register 20
R/W
0
0
1
0
1
0
0
X
SRST
1
X
MONO
CHSL
OS1
OS0
Register 21
R
0
0
1
0
1
0
1
X
X
X
X
X
DZ1
DZ0
X
Register 22
R
0
0
1
0
1
1
0
X
X
X
X
X
X
ZFGR
ZFGL
(1)
Function is disabled. No operation even if data bit is set.
44
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): PCM1795



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