ZL2008 datasheet(17/47 Pages) INTERSIL

17 / 47 page

ZL2008

Data Sheet Revision 2/19/2009

www.intersil.com

Figure 12. RSET on a POLA Module

The POLA mode is activated through pin-strap by

connecting a 110 kΩ resistor on V0 to SGND. The V1

pin is then used to adjust the output voltage as shown

in Table 8.

The POLA mode can also be activated through PMBus

commands. See Application Note AN33 for more

details.

Table 8. POLA Mode VOUT Settings

(R0 = 110 kΩ, R1 = RSET + 10 kΩ)

VOUT

RSET

In series with

10kΩ resistor

VOUT

RSET

In series with

10kΩ resistor

0.700 V

162 k

0.991 V

21.5 k

0.752 V

110 k

1.000 V

19.6 k

0.758 V

100 k

1.100 V

16.2 k

0.765 V

90.9 k

1.158 V

13.3 k

0.772 V

82.5 k

1.200 V

12.1 k

0.790 V

75.0 k

1.250 V

9.09 k

0.800 V

56.2 k

1.500 V

7.50 k

0.821 V

51.1 k

1.669 V

5.62 k

0.834 V

46.4 k

1.800 V

4.64 k

0.848 V

42.2 k

2.295 V

2.87 k

0.880 V

34.8 k

2.506 V

2.37 k

0.899 V

31.6 k

3.300 V

1.21 k

0.919 V

28.7 k

5.000 V

0.162 k

0.965 V

23.7 k

5.3.4. DOSA Voltage Trim Mode

On a DOSA module, the VOUT setting follows this

equation:

OUT

SET

6900

−

To maintain DOSA compatibility, the same scheme is

used as with a POLA module except the 10 kΩ resistor is

replaced with a 8.66 kΩ resistor as shown in Figure 13.

8.66 kΩ

DOSA

MODULE

Rset

110 kΩ

Figure 13. RSET on a DOSA Module

The DOSA mode VOUT settings are listed in Table 9.

Table 9. DOSA Mode VOUT Settings

(R0 = 110 kΩ, R1 = RSET + 8.66 kΩ)

VOUT

RSET

In series with

8.66kΩ

resistor

VOUT

RSET

In series with

8.66kΩ

resistor

0.700 V

162 k

0.991 V

22.6 k

0.752 V

113 k

1.000 V

21.0 k

0.758 V

100 k

1.100 V

17.8 k

0.765 V

90.9 k

1.158 V

14.7 k

0.772 V

82.5 k

1.200 V

13.3 k

0.790 V

75.0 k

1.250 V

10.5 k

0.800 V

57.6 k

1.500 V

8.87 k

0.821 V

52.3 k

1.669 V

6.98 k

0.834 V

47.5 k

1.800 V

6.04 k

0.848 V

43.2 k

2.295 V

4.32 k

0.880 V

36.5 k

2.506 V

3.74 k

0.899 V

33.2 k

3.300 V

2.61 k

0.919 V

30.1 k

5.000 V

1.50 k

0.965 V

25.5 k

5.4 Start-up Procedure

The ZL2008 follows a specific internal start-up

procedure after power is applied to the VDD pin. Table

10 describes the start-up sequence.

If the device is to be synchronized to an external clock

source, the clock frequency must be stable prior to

asserting

the

pin.

The

device

requires

approximately 5-10 ms to check for specific values

stored in its internal memory. If the user has stored

values in memory, those values will be loaded. The

device will then check the status of all multi-mode pins

and load the values associated with the pin settings.

ZL2008 Datasheet(PDF) 17 Page - Intersil Corporation

ZL2008 Datasheet(HTML) 17 Page - Intersil Corporation

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