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LTC3620 Datasheet(PDF) 3 Page - Linear Technology

Part # LTC3620
Description  Ultralow Power 15mA Synchronous Step-Down Switching Regulator
PDF  16 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC3620 Datasheet(HTML) 3 Page - Linear Technology

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LTC3620
3
3620f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: TJ is calculated from the ambient temperature, TA, and power
dissipation, PD, according to the following formula:
TJ = TA + (PD)(88.5°C/W)
Note 3: The LTC3620 is tested in a proprietary test mode that connects VFB
to the output of the error amplifier.
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VFMIN
FMIN/MODE Input Voltage High
0.9
V
FMIN/MODE Input Voltage Low
0.7
V
fEXT
FMIN/MODE Input Frequency
20
300
kHz
IFMIN/MODE
FMIN/MODE Pin Leakage Current
±0.01
±1
μA
ISW
Switch Leakage Current
VRUN = 0V, VSW = 0V or 5.5V, VIN = 5.5V
±0.01
±1
μA
IFB
VFB Pin Current
LTC3620, VFB = 0.6V
LTC3620-1, VFB = 1.1V
0
1.2
±30
2.0
nA
μA
VUVLO
Undervoltage Lockout (UVLO)
VIN Decreasing
2.7
2.8
2.9
V
VLOBATB
LOBATB Threshold
VIN Decreasing
2.93
3.0
3.08
V
RLOBATB
LOBATB Pull-Down On-Resistance
15
Ω
VHLOBATB
LOBATB Hysteresis
100
mV
RPFET
RDS(ON) of P-channel FET (Note 5)
ISW = 50mA, VIN = 3.6V
2.0
Ω
RNFET
RDS(ON) of N-channel FET (Note 5)
ISW = –50mA, VIN = 3.6V
1.0
Ω
Note 4: The LTC3620E is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 85°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls.
Note 5: The DFN switch-on resistance is guaranteed by correlation to
wafer level measurements.



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