LTM9003 datasheet(14/24 Pages) LINER

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LTM9003

9003p

inputs are both single ended. Low side or high side LO

injection can be used.

The mixer’s RF input consists of an integrated transformer

and a high linearity differential ampliﬁer. The primary

terminals of the transformer are connected to the RF

input (Pin G1) and ground. The secondary side of the

transformer is internally connected to the ampliﬁer’s dif-

ferential inputs.

The mixer’s LO input consists of an integrated transformer

and high speed limiting differential ampliﬁers. The ampli-

ﬁers are designed to precisely drive the mixer for the

highest linearity and the lowest noise ﬁgure.

Wideband Filter

Most of the IF ﬁltering is done between the mixer and

the IF ampliﬁer. This network is a 2nd order Chebychev

bandpass section, designed for 0.1dB passband ripple.

The 3dB bandwidth is 220MHz, centered at 184MHz, see

Figure 3. Additional lowpass ﬁltering is done just before

the ADC. This ﬁlter serves to bandlimit the out of band

noise entering the converter, as well as to isolate the

output of the IF ampliﬁer from the sampling action of the

converter.

IF FREQUENCY (MHz)

210

310

160

110

260

360

9003 F03

410

–20

–40

–10

–5

–30

–25

–15

–35

–45

–50

Figure 3. IF Filter Response

Analog to Digital Converter

As shown in Figure 1, the analog-to-digital converter (ADC)

is a CMOS pipelined multistep converter. The converter

has ﬁve pipelined ADC stages; a sampled analog input will

result in a digitized value ﬁve cycles later (see the Tim-

ing Diagram section). The encode input is differential for

improved common mode noise immunity. The ADC has

two phases of operation, determined by the state of the

differential ENC+/ENC– input pins. For brevity, the text will

refer to ENC+ greater than ENC– as ENC high and ENC+

less than ENC– as ENC low.

Each pipelined stage shown in Figure 1 contains an ADC,

a reconstruction DAC and an interstage residue ampliﬁer.

In operation, the ADC quantizes the input to the stage and

the quantized value is subtracted from the input by the

DAC to produce a residue. The residue is ampliﬁed and

output by the residue ampliﬁer. Successive stages operate

out of phase so that when the odd stages are outputting

their residue, the even stages are acquiring that residue

and visa versa.

When ENC is low, the analog input is sampled differentially

directly onto the input sample-and-hold capacitors, inside

the “Input S/H” shown in the Block Diagram. At the instant

that ENC transitions from low to high, the sampled input is

held. While ENC is high, the held input voltage is buffered

by the S/H ampliﬁer which drives the ﬁrst pipelined ADC

stage. The ﬁrst stage acquires the output of the S/H dur-

ing this high phase of ENC. When ENC goes back low, the

ﬁrst stage produces its residue which is acquired by the

second stage. At the same time, the input S/H goes back

to acquiring the analog input. When ENC goes back high,

the second stage produces its residue which is acquired

by the third stage. An identical process is repeated for the

third and fourth stages, resulting in a fourth stage residue

that is sent to the ﬁfth stage ADC for ﬁnal evaluation.

Each ADC stage following the ﬁrst has additional range to

accommodate ﬂash and ampliﬁer offset errors. Results

from all of the ADC stages are digitally synchronized such

that the results can be properly combined in the correction

logic before being sent to the output buffer.

OPERATION

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