LTM9003 datasheet(18/24 Pages) LINER

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LTM9003

9003p

VDD

LTM9003

9003 F08

VDD

ENC–

ENC+

1.5V

BIAS

1.5V

BIAS

0.1μF

MA/COM

ETC1-1-13

CLOCK

INPUT

100Ω

8.2pF

0.1μF

50Ω

•

50Ω

4.8k

TO INTERNAL

ADC CIRCUITS

APPLICATIONS INFORMATION

Maximum and Minimum Conversion Rates

The maximum conversion rate for the ADC is 250Msps.

For the ADC to operate properly, the encode signal should

have a 50% (±5%) duty cycle. Each half cycle must have

at least 1.9ns for the ADC internal circuitry to have enough

settling time for proper operation. Achieving a precise 50%

duty cycle is easy with differential sinusoidal drive using

a transformer or using symmetric differential logic such

as PECL or LVDS.

The lower limit of the sample rate is determined by the

droop of the sample-and-hold circuits. The pipelined ar-

chitecture of this ADC relies on storing analog signals on

small valued capacitors. Junction leakage will discharge

the capacitors. The speciﬁed minimum operating frequency

for the LTM9003 is 1Msps.

Clock Duty Cycle Stabilizer

An optional clock duty cycle stabilizer circuit can be used if

the input clock has a non 50% duty cycle. This circuit uses

the rising edge of the ENC+ pin to sample the analog input.

The falling edge of ENC+ is ignored and the internal falling

edge is generated by a phase-locked loop. The input clock

duty cycle can vary from 40% to 60% and the clock duty

cycle stabilizer will maintain a constant 50% internal duty

cycle. If the clock is turned off for a long period of time,

the duty cycle stabilizer circuit will require one hundred

clock cycles for the PLL to lock onto the input clock. To

use the clock duty cycle stabilizer, the MODE pin should be

connected to 1/3VDD or 2/3VDD using external resistors.

Clock Sources for Undersampling

Undersampling is especially demanding on the clock source

and the higher the input frequency, the greater the sensitivity

to clock jitter or phase noise. A clock source that degrades

SNR of a full-scale signal by 1dB at 70MHz will degrade

SNR by 3dB at 140MHz, and 4.5dB at 190MHz.

In cases where absolute clock frequency accuracy is

relatively unimportant and only a single ADC is required, a

canned oscillator from vendors such as Saronix or Vectron

can be placed close to the ADC and simply connected

directly to the ADC. If there is any distance to the ADC,

some source termination to reduce ringing that may occur

even over a fraction of an inch is advisable. You must not

allow the clock to overshoot the supplies or performance

will suffer. Do not ﬁlter the clock signal with a narrow band

ﬁlter unless you have a sinusoidal clock source, as the

rise and fall time artifacts present in typical digital clock

signals will be translated into phase noise.

Figure 8. Transformer Driven ENC+/ENC–

Figure 9. Single-Ended ENC Driver, Not Recommended

for Low Jitter

Figure 10. ENC Drive Using LVDS

9003 F09

ENC–

1.5V

VTHRESHOLD = 1.5V

ENC+

0.1μF

LTM9003

9003 F10

ENC–

ENC+

LVDS

CLOCK

100Ω

0.1μF

LTM9003

0.1μF

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