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DS3105 Datasheet(PDF) 75 Page - Maxim Integrated Products |
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DS3105 Datasheet(HTML) 75 Page - Maxim Integrated Products |
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75 / 120 page  _____________________________________________________________________________________________ DS3105 19-4628; Rev 3; 5/09 75 of 120 Register Name: DIVN1 Register Description: DIVN Register 1 Register Address: 46h Bit # 7 6 5 4 3 2 1 0 Name DIVN[7:0] Default 1 1 1 1 1 1 1 1 Note: The DIVN1 and DIVN2 registers must be read consecutively and written consecutively. See Section 8.3. Bits 7 to 0: DIVN Factor (DIVN[7:0]). The full 16-bit DIVN[15:0] field spans this register and DIVN2. This field contains the integer value used to divide the frequency of input clocks that are configured for DIVN mode. The frequency is divided by DIVN[15:0] + 1. See Section 7.4.2.4. Register Name: DIVN2 Register Description: DIVN Register 2 Register Address: 47h Bit # 7 6 5 4 3 2 1 0 Name DIVN[15:8] Default 0 0 1 1 1 1 1 1 Bits 7 to 0: DIVN Factor (DIVN[15:8]). See the DIVN1 register description. |
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