CS5530 datasheet(17/36 Pages) CIRRUS

17 / 36 page

CS5530

DS742F2

2.2.4 Reading/Writing On-Chip Registers

The CS5530’s offset, gain, and configuration regis-

ters are readable and writable while the conversion

data register is read only.

As shown in Figure 7, to write to a particular regis-

ter the user must transmit the appropriate write

command and then follow that command by 32 bits

of data. For example, to write 0x80000000 (hexa-

decimal) to the gain register, the user would first

transmit the command byte 0x02 (hexadecimal)

followed by the data 0x80000000 (hexadecimal).

Similarly, to read a particular register the user must

transmit the appropriate read command and then

acquire the 32 bits of data. Once a register is written

to or read from, the serial port returns to the com-

mand mode.

2.3 Configuration Register

To ease the architectural design and simplify the

serial interface, the configuration register is thirty-

two bits long, however, only fifteen of the thirty

two bits are used. The following sections detail the

bits in the configuration register.

2.3.1 Power Consumption

The CS5530 accommodates three power consump-

tion modes: normal, standby, and sleep. The default

mode, “normal mode”, is entered after power is ap-

plied. In this mode, the CS5530 typically consumes

35 mW. The other two modes are referred to as the

power save modes. They power down most of the

analog portion of the chip and stop filter convolu-

tions. The power save modes are entered whenever

the power down (PDW) bit of the configuration

mode entered depends on state of the PSS (Power

Save Select) bit. If PSS is logic 0, the converter en-

ters the standby mode reducing the power con-

sumption to 4 mW. The standby mode leaves the

oscillator and the on-chip bias generator for the an-

alog portion of the chip active. This allows the con-

verter to quickly return to the normal mode once

PDW is set back to a logic 0. If PSS and PDW are

both set to logic 1, the sleep mode is entered reduc-

ing the consumed power to around 500

μW. Since

this sleep mode disables the oscillator, approxi-

mately a 20 ms oscillator start-up delay period is

required before returning to the normal mode. If an

external clock is used, there will be no delay.

2.3.2 System Reset Sequence

The reset system (RS) bit permits the user to per-

form a system reset. A system reset can be initiated

at any time by writing a logic 1 to the RS bit in the

configuration register. After the RS bit has been

set, the internal logic of the chip will be initialized

to a reset state. The reset valid (RV) bit is set indi-

cating that the internal logic was properly reset.

The RV bit is cleared after the configuration regis-

ter is read. The on-chip registers are initialized to

the following default states:

After reset, the RS bit should be written back to

logic 0 to complete the reset cycle. The ADC will

return to the command mode where it waits for a

valid command. Also, the RS bit is the only bit in

the configuration register that can be set when ini-

tiating a reset (i.e. a second write command is need-

ed to set other bits in the Configuration Register

after the RS bit has been cleared).

2.3.3 Input Short

The input short bit allows the user to internally

ground the inputs of the ADC. This is a useful func-

tion because it allows the user to easily test the

grounded input performance of the ADC and elim-

inate the noise effects due to the external system

components.

2.3.4 Voltage Reference Select

The voltage reference select (VRS) bit selects the

size of the sampling capacitor used to sample the

voltage reference. The bit should be set based upon

Configuration Register:

00000000(H)

Offset Register:

00000000(H)

Gain Register

01000000(H)

CS5530 Datasheet(PDF) 17 Page - Cirrus Logic

CS5530 Datasheet(HTML) 17 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL