CS8422 datasheet(36/82 Pages) CIRRUS

36 / 82 page

DS692PP2

CS8422

RCBL (out)

VLRCK (out)

C/U (out)

C/U[0]

C/U[1]

C/U[383]

192 AES3 Frames

Figure 19. C/U Data Outputs

Note:

RCBL will go high on the transition of the first output C/U data bit (C/U[0]) and will remain high until the C/U[0] - C/U[1] transition.

VLRCK is a virtual word clock that is available through the GPO pins, and can be used to frame the C/U output.

VLRCK frequency is always equal to the incoming frame rate of the AES3-compatible data. If there are an even number of OSCLK

periods per OLRCK, then the VLRCK duty cycle is 50%, otherwise it is 50% ± one OSCLK period.

If a serial audio output port is sourced directly by the AES3-compatible receiver VLRCK = OLRCK in I²S Mode, and

VLRCK = OLRCK in left-justified and Right-Justified Modes.

If a serial port is sourced directly by the AES3-compatible receiver, the data will transition on the fourth OSCLK falling edge after a

VLRCK edge and will be valid on VLRCK edges (t = 4 OSCLK period).

If a serial port is not sourced directly by the AES3-compatible receiver (as in a sample rate conversion application), the data will

transition 1/64*Fsi after a VLRCK edge, and will be valid on VLRCK edges (t = 1/64*Fsi).

CS8422 Datasheet(PDF) 36 Page - Cirrus Logic