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AD7191

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tolerant to decoupling capacitors on REFIN(+) without

introducing gain errors in the system. Deriving the reference

input voltage across an external resistor means that the

reference input sees a significant external source impedance.

External decoupling on the REFIN pins is not recommended in

this type of circuit configuration.

DIGITAL INTERFACE

The serial interface of the AD7191 consists of two signals: SCLK

and DOUT/RDY. SCLK is the serial clock input for the device,

and data transfers occur with respect to the SCLK signal. The

DOUT/RDY pin is dual purpose: it functions as a data ready pin

and as a data output pin. DOUT/RDY goes low when a new

data-word is available in the output register. A 24-bit word is

placed on the DOUT/RDY pin when sufficient SCLK pulses are

applied.

DOUT/RDY is reset high when the conversion has been read. If

the conversion is not read, DOUT/RDY goes high prior to the

next data register update to indicate when not to read from the

device. This ensures that a read operation is not attempted while

the register is being updated. Each conversion can be read only

once. The data register is updated for every conversion. Thus,

when a conversion is complete, the serial interface is reset, and

the new conversion is placed in the data register. Therefore, the

user must ensure that the complete word is read before the next

conversion is complete.

When PDOWN is high, the DOUT/RDY pin is tristated. When

PDOWN is taken low, the internal clock requires 1 ms approx-

imately to power up. Following this, the ADC continuously

converts. The first conversion requires the complete settling

time. DOUT/RDY goes high when PDOWN is taken low and

returns low only when a conversion is available. The ADC then

converts continuously, and subsequent conversions are available

at the selected output data rate.

shows the timing for a

read operation from the AD7191.

Figure 3

When the output data rate, gain, channel, or clock source is

changed, the modulator and filter are reset immediately.

DOUT/RDY is set high.

The ADC then begins conversions using the new configuration.

DOUT/RDY remains high until the appropriate settling time

for the filter elapses. Therefore, any read operations should be

completed before changing the operating conditions or channel.

Otherwise, all 1s are read back from the AD7191 as the

DOUT/RDY pin is set high following the channel change or

configuration change.

GROUNDING AND LAYOUT

Because the analog inputs and reference input on the AD7191

are differential, most of the voltages in the analog modulator

are common-mode voltages. The excellent common-mode reject-

tion of the part removes common-mode noise on these inputs.

The analog and digital supplies to the AD7191 are independent

and separately pinned out to minimize coupling between the

analog and digital sections of the device. The AD7191 can be

operated with 5 V analog and 3 V digital supplies or vice versa.

The digital filter provides rejection of broadband noise on the

power supplies, except at integer multiples of the modulator

sampling frequency. A simple R-C low-pass filter on the analog

inputs rejects any interference at the clock frequency. The

digital filter also removes noise from the analog and reference

inputs, provided that these noise sources do not saturate the

analog modulator. As a result, the AD7191 is more immune to

noise interference than a conventional high resolution

converter. However, because the resolution of the AD7191 is so

high, and the noise levels from the AD7191 are so low, care

must be taken with regard to grounding and layout.

The printed circuit board should be designed such that the

analog and digital sections are separated and confined to

certain areas of the board. This facilitates the use of ground

planes that can be easily separated. A minimum etch technique

is generally best for ground planes because it gives the best

shielding.

Although the AD7191 has separate pins for analog and digital

ground, the AGND and DGND pins are tied together within

the device via the substrate. The user must not tie these pins

externally to separate ground planes unless the ground planes

are connected together near the AD7191.

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