AD7985 datasheet(13/28 Pages) AD

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AD7985

Rev. 0 | Page 13 of 28

THEORY OF OPERATION

COMP

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNV

CONTROL

LOGIC

SW+

LSB

SW–

LSB

IN+

REF

REFGND

IN–

MSB

16,384C

32,768C

16,384C

32,768C

Figure 21. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7985 is a fast, low power, single-supply, precise, 16-bit

ADC using a successive approximation architecture. The AD7985

features different modes to optimize performance according to the

application. In turbo mode, the AD7985 is capable of converting

2,500,000 samples per second (2.5 MSPS).

The AD7985 provides the user with an on-chip track-and-hold

and does not exhibit any pipeline delay or latency, making it

ideal for multiple multiplexed channel applications.

The AD7985 can be interfaced to any 1.8 V to 2.7 V digital logic

family. It is available in a space-saving 20-lead LFCSP that allows

flexible configurations. It is pin-for-pin compatible with the

18-bit AD7986.

CONVERTER OPERATION

The AD7985 is a successive approximation ADC based on a

charge redistribution DAC. Figure 21 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 16 binary-weighted capacitors that are

connected to the two comparator inputs.

During the acquisition phase, the terminals of the array tied to

the input of the comparator are connected to AGND via SW+

and SW−. All independent switches are connected to the analog

inputs. Therefore, the capacitor arrays are used as sampling

capacitors and acquire the analog signal on the IN+ and IN−

inputs. When the acquisition phase is completed and the CNV

input goes high, a conversion phase is initiated.

When the conversion phase begins, SW+ and SW− are opened

first. The two capacitor arrays are then disconnected from the

analog inputs and connected to the REFGND input. Therefore,

the differential voltage between the IN+ and IN− inputs captured

at the end of the acquisition phase is applied to the comparator

inputs, causing the comparator to become unbalanced. By switch-

ing each element of the capacitor array between REFGND and

REF, the comparator input varies by binary-weighted voltage

steps (VREF/2, VREF/4

, … VREF/65,536). The control logic toggles

these switches, starting with the MSB, to bring the comparator

back into a balanced condition. After the completion of this

process, the part returns to the acquisition phase, and the control

logic generates the ADC output code and a busy signal indicator.

Because the AD7985 has an on-board conversion clock, the

serial clock, SCK, is not required for the conversion process.

CONVERSION MODES OF OPERATION

The AD7985 features two conversion modes of operation: turbo

and normal. Turbo conversion mode (TURBO is high) allows

the fastest conversion rate of up to 2.5 MSPS and does not

power down between conversions. The first conversion in turbo

mode should be ignored because it contains meaningless data.

For applications that require lower power and slightly slower

sampling rates, the normal mode (TURBO is low) allows a

maximum conversion rate of 2.0 MSPS and powers down

between conversions. The first conversion in normal mode

contains meaningful data.

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