XRT86VL3X datasheet(52/154 Pages) EXAR

52 / 154 page

XRT86VL3X

T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

REV. 1.2.3

4.5

E1 Receive Overhead Interface

4.5.1

Description of the E1 Receive Overhead Output Interface Block

The E1 Receive Overhead Output Interface Block will allow an external device to be the consumer of the E1

National bit sequence. This interface provides interface signals and required interface timing to shift out proper

data link information at proper time.

The Receive Overhead Output Interface for a given Framer consists of two signals.

• RxOHClk_n: The Receive Overhead Output Interface Clock Output signal

• RxOH_n: The Receive Overhead Output Interface Output signal.

The Receive Overhead Output Interface Clock Output pin (RxOHCLK_n) generates a rising clock edge for

each National bit that is configured to carry Data Link information according to setting of the framer. The data

link bits extracted from the incoming E1 frames are outputted from the Receive Overhead Output Interface

Output pin (RxOH_n) before the rising edge of RxOHClk_n. The Data Link equipment should sample and latch

the data link bits at the rising edge of RxOHClk_n.

The figure below shows block diagram of the Receive Overhead Output Interface of XRT86VL3x.

4.5.2

Configure the E1 Receive Overhead Output Interface module as source of the National Bit

Sequence in E1 framing format mode

The National Bit Sequence in E1 framing format mode can be extracted and directed to:

• E1 Receive Overhead Output Interface Block

• E1 Receive HDLC Controller

• E1 Receive Serial Output Interface

The purpose of the Receive Overhead Output Interface is to permit Data Link equipment to have direct access

to the Sa4 through Sa8 National bits that are extracted from the incoming E1 frames. Independent of the

availability of the E1 Receive HDLC Controller module, the XRT86VL3x always output the received National

bits through the Receive Overhead Output Interface block.

The XRT86VL3x allows the user to decide on the following:

• How many of the National Bits is used to carry the Data Link information bits

• Which of these National Bits is used to carry the Data Link information bits.

The Receive Sa Data Link Select bits of the Receive Signaling and Data Link Select Register (TSDLSR)

determine which ones of the National bits are configured as Data Link bits in E1 framing format mode.

Depending upon the configuration of the Receive Signaling and Data Link Select Register, either of the

following cases may exists:

• None of the received National bits are used to transport the Data Link information bits (That is, data link

channel of XRT86VL3x is inactive).

• Any combination of between 1 and all 5 of the received National bits are used to transport the Data Link

information bits.

FIGURE 44. BLOCK DIAGRAM OF THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE OF XRT86VL3X

Receive

Overhead Output

Interface

RxOH_n

RxOHClk_n

From Receive

Framer Block

XRT86VL3X Datasheet(PDF) 52 Page - Exar Corporation

XRT86VL3X Datasheet(HTML) 52 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL