XRT86VL3X datasheet(74/154 Pages) EXAR

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XRT86VL3X

T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

REV. 1.2.3

E1 Receive Multiplexed Mode

The interface consists of the following pins:

• Data Output (RxSer_n)

• Receive Serial Clock Input signal (RxSerClk_n)

• Receive Single-frame Synchronization Input signal (RxSync_n)

The Receive Back-plane Interface is pumping out data through RxSer_0 or RxSer_4 pins at 16.384Mbit/s. It

multiplexes payload and signaling data of every four channels into one data stream. Payload and signaling

data of Channel 0-3 are multiplexed onto the Receive Serial Data pin of Channel 0. Payload and signaling data

of Channel 4-7 are multiplexed onto the Receive Serial Data pin of Channel 4.

Free-running clocks of 16.384MHz are supplied to the Receive Serial Clock pin of Channel 0 and Channel 4 of

the framer. The Receive High-speed Back-plane Interface of the farmer provides data at rising edge of this

Receive Serial Clock. The local Terminal Equipment then latches incoming serial data at falling edge of the

clock. Figure 72 shows the interface of the Recieve Payload Data Output Interface Block to the Terminal

Equipment.

The multiplexed data output on RxSER_0 or RxSER_4 are very similar to the Multiplexed data input on

TxSER_0 or TxSER_4 except when the receive framer is running at 16MHz Bit-Multiplexed mode. When the

receive framer is running at 16MHz Bit-Multiplexed mode, the multiplexed data on RxSER_0 or RxSER_4 are

return-to-zero data when the receive framer is processing the first four bits of each time slot data of each

channel, as shown in Figure . Figure shows the timing signal when the receive framer is running at HMVIP or

H.100 16.384 MHz mode.

FIGURE 71. WAVEFORMS FOR CONNECTING THE TRANSMIT MULTIPLEXED HIGH-SPEED INPUT INTERFACE AT

HMVIP AND H.100 16.384MBIT/S MODE

TxInClk (16.384MHz)

TxInClk (INV)

TxSer

2 52

0 10 20 20

0 50 60 60

3 73 83 83

0 h0 h0 h0

56 cycles

3 53 63 63 73 73 83 83

2 A2

0 0 0 0

0 B0

3C3D3D3

1 1 1 1

56 cycles

3 A3 B3 B3C3C3D3D3

TxSig

TxSync(input)

HMVIP, negative sync

TxSync(input)

HMVIP, positive sync

Start of Frame

y : X is the bit number and y is the channel number

TxSync(input)

H.100, negative sync

TxSync(input)

H.100, positive sync

Delayer H.100

TxSync(input)

H.100, negative sync

TxSync(input)

H.100, positive sync

XRT86VL3X Datasheet(PDF) 74 Page - Exar Corporation

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