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STM8L151C4 Datasheet(PDF) 88 Page - STMicroelectronics |
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STM8L151C4 Datasheet(HTML) 88 Page - STMicroelectronics |
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88 / 101 page  Electrical parameters STM8L151xx, STM8L152xx 88/101 Doc ID 15962 Rev 2 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 19 or Figure 20, depending on whether VREF+ is connected to VDDA or not. Good quality ceramic 10 nF capacitors should be used. They should be placed as close as possible to the chip. Figure 19. Power supply and reference decoupling (VREF+ not connected to VDDA) Table 47. ADC1 accuracy Symbol Parameter Typ Max(1) Unit DNL Differential non linearity TBD ± 1 LSB INL Integral non linearity TBD ± 2 LSB TUE Total unadjusted error TBD ± 5 LSB Offset Offset error TBD ± 2 LSB Gain Gain error TBD ± 3.5 LSB ENOB Effective number of bits TBD ± 9.5 Bits SINAD Signal-to-noise and distortion ratio TBD TBD dB SNR Signal-to-noise ratio TBD TBD dB THD Total harmonic distorsion TBD TBD dB 1. Data based on characterization, not tested in production. V REF+ STM8L V DDA V SSA/V REF- 1 µF // 10 nF 1 µF // 10 nF ai17031 |
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