LP4062 datasheet(9/13 Pages) POWER

9 / 13 page

Preliminary

Datasheet

LP4062

LP4062 –00

Ver. 1.0 Datasheet

Nov.-2007

Page 9 of 13

approximately 120 ℃ . This feature protects the

LP4062 from excessive temperature and allows

the user to push the limits of the power handling

capability of a given circuit board without risk of

damaging the LP4062. The charge current can be

set according to typical (not worst-case) ambient

temperature with the assurance that the charger

will automatically reduce the current in worst-case

conditions. ThinSOT power considerations are

discussed further in the Applications Information

section.

Undervoltage Lockout (UVLO)

An internal undervoltage lockout circuit monitors the

input voltage and keeps the charger in shutdown mode

until VCC rises above the undervoltage lockout

threshold .The UVLO circuit has a built-in hysteresis

of 200mV. Furthermore, to protect against reverse

current in the power MOSFET, the UVLO circuit

keeps the charger in shutdown mode if VCC falls to

within 30mV of the battery voltage. If the UVLO

comparator is tripped, the charger will not come out of

shutdown mode until VCC rises 100mV above the

battery voltage.

Manual Shutdown

At any point in the charge cycle, the LP4062 can be

put into shutdown mode by removing RPROG thus

floating the PROG pin. This reduces the battery drain

current to less than 2µA and the supply current to less

than 50µA. A new charge cycle can be initiated by

reconnecting the program resistor. In manual shutdown,

the CHRG pin is in a weak pull-down state as long as

VCC is high enough to exceed the UVLO conditions.

The CHRG pin is in a high impedance state if the

LP4062 is in under voltage lockout mode: either VCC

is within 100mV of the BAT pin voltage or insufficient

voltage is applied to the VCC pin.

Automatic Recharge

Once the charge cycle is terminated, the LP4062

continuously monitors the voltage on the BAT pin

using a comparator with a 2ms filter time

(TRECHARGE). A charge cycle restarts when the

battery voltage falls below 4.05V (which corresponds

to approximately 80% to 90% battery capacity). This

ensures that the battery is kept at or near a fully

charged condition and eliminates the need for periodic

charge cycle initiations. CHRG output enters a strong

pull-down state during recharge cycles.

Application Information

Stability Considerations

The constant-voltage mode feedback loop is stable

without an output capacitor provided a battery is

connected to the charger output. With no battery

present, an output capacitor is recommended to reduce

ripple voltage. When using high value, low ESR

ceramic capacitors, it is recommended to add a 1Ω

resistor in series with the capacitor. No series resistor

is needed if tantalum capacitors are used. In

constant-current mode, the PROG pin is in the

feedback loop, not the battery. The constant-current

mode stability is affected by the impedance at the

PROG pin. With no additional capacitance on the

PROG pin, the charger is stable with program resistor

values as high as 20k. However, additional capacitance

on this node reduces the maximum allowed program

resistor. The pole frequency at the PROG pin should be

kept above 100kHz. Therefore, if the PROG pin is

loaded with a capacitance, PROG, the following

equation can be used to calculate the maximum

resistance value for RPROG:

LP4062 Datasheet(PDF) 9 Page - Lowpower Semiconductor inc

LP4062 Datasheet(HTML) 9 Page - Lowpower Semiconductor inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13

Datasheet Download

Link URL