IMX35 datasheet(16/148 Pages) FREESCALE

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i.MX35 Applications Processors for Automotive Products, Rev. 6

Freescale Semiconductor

4.1.2

Interface Frequency Limits

Table 9 provides information on interface frequency limits.

4.2

Power Modes

Table 10 provides descriptions of the power modes of the i.MX35 processor.

Table 9. Interface Frequency

Parameter

Symbol

Min.

Typ.

Max.

Units

JTAG TCK Frequency

fJTAG

MHz

Table 10. i.MX35 Power Modes

Power

Mode

Description

QVCC (ARM/L2

Peripheral)

MVDD/PVDD

OSC24M_VDD

OSC_AUDO_VDD

Typ.

Max.

Typ.

Max.

Typ.

Max.

Wait

VDD1,2,3,4 = 1.1 V (min.)

ARM is in wait for interrupt mode.

MAX is active.

L2 cache is kept powered.

MCU PLL is on (400 MHz)

PER PLL is off (can be configured)

(default: 300 MHz)

Module clocks are gated off (can be

configured by CGR register).

OSC 24M is ON.

OSC audio is off (can be configured).

RNGC internal osc is off.

170

7.2 mA

1.2

Doze

VDD1,2,3,4 = 1.1 V (min.)

ARM is in wait for interrupt mode.

MAX is halted.

L2 cache is kept powered.

L2 cache control logic off.

AWB enabled.

MCU PLL is on(400 MHz)

PER PLL is off (can be configured).

(300 Mhz).

Module clocks are gated off (can be

configured by CGR register).

OSC 24M is ON.

OSC audio is off (can be configured)

RNGC internal osc is off

12.4 mA

105 mA

7.2 mA

14 mA

1.2 mA

3 mA

IMX35 Datasheet(PDF) 16 Page - Freescale Semiconductor, Inc

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