MPC5668X datasheet(57/66 Pages) FREESCALE

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Electrical Characteristics

MPC5668x Microcontroller Data Sheet, Rev. 3

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

Figure 25. Media Local Bus (MLB) Timing

4.14.8

Fast Ethernet Interface

MII signals use CMOS signal levels compatible with devices operating at either 5.0 V or 3.3 V. Signals are not TTL compatible.

They follow the CMOS electrical characteristics.

4.14.8.1

MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)

The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency

requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency.

1 The Controller can shut off MLBCLK to place MLB in a low-power state.

2 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other

edge, measured in ns peak-to-peak (ns p-p).

3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this

time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.

Table 33. MII Receive Signal Timing

Spec

Characteristic

Min

Max

Unit

RXD[3:0], RX_DV, RX_ER to RX_CLK setup

—

RX_CLK to RXD[3:0], RX_DV, RX_ER hold

—

RX_CLK pulse width high

35%

65%

RX_CLK period

RX_CLK pulse width low

35%

65%

RX_CLK period

MLBCLK

MLBSIG/

MLBDAT

(output)

valid data

MLBSIG/

MLBDAT

(input)

MPC5668X Datasheet(PDF) 57 Page - Freescale Semiconductor, Inc

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