SC9641

HANGZHOU SILAN MICROELECTRONICS CO.,LTD

REV:1.0

2008.03.24

Http: www.silan.com.cn

Page 13 of 15

5. PARALLEL COMMUNICATION TIMING WAVEFORM

Note: WR (pin 31), RD (pin 32) is controlled by system (master controller), and ACK (pin 28) is controlled by

SC9641 (sub-controller), normal state is high level, and DATA is controlled by all above.

1) Write mode: ACK_H

a. The system set WR: begin to write operation: MSB (T1).

b. The system wait SC9641 acknowledge: MSB (T2)

c. After the system write data to the DATA port, set the WR: LSB (T3).

d. The system wait for the response of SC9641: LSB (T4)

(After SC9641 read the data, set ACK: LSB)

e. After write one byte, according to the a

→ b → c → d order write the next byte.

2) Read mode: ACK_H

a. The system set RD: MSB (T1), and begin to read operation.

b. The system wait for SC9461 response ACK: MSB (T2) (SC9641 set ACK after data ready:

MSB)

c. After the system read out the data, set the RD: LSB (T3).

d. The system wait for the response of SC9641: LSB (T4).

e. After read one byte, according to the a

→ b → c → d order perform the next byte read

operation.

3) Time of communication protocol:

a. system read (SYS READ):

T2-T1: >=7us

T3-T2: =5us (TYP.), related with the execute speed of master controller.

T4-T3: >=6us