56F8366 datasheet(25/182 Pages) FREESCALE

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Signal Pins

56F8366 Technical Data, Rev. 7

Freescale Semiconductor

Preliminary

(CS1)

(GPIOD9)

Output

Input/

Output

In reset,

output is

disabled,

pull-up is

enabled

Data Memory Select — This signal is actually CS1 in the EMI,

which is programmed at reset for compatibility with the 56F80x DS

signal. DS is asserted low for external data memory access.

Depending upon the state of the DRV bit in the EMI bus control

CS1 resets to provide the DS function as defined on the 56F80x

devices.

Port D GPIO — This GPIO pin can be individually programmed as

an input or output pin.

To deactivate the Internal pull-up resistor, clear bit 9 in the

GPIOD_PUR register.

GPIOD0

(CS2)

(CAN2_TX)

Input/

Output

Open

Drain

Output

Input,

pull-up

enabled

Port D GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Chip Select — CS2 may be programmed within the EMI module to

act as a chip select for specific areas of the external memory map.

Depending upon the state of the DRV bit in the EMI Bus Control

Most designs will want to change the DRV state to DRV = 1 instead of

using the default setting.

FlexCAN2 Transmit Data — CAN output.

At reset, this pin is configured as GPIO. This configuration can be

changed by setting bit 0 in the GPIO_D_PER register. Then

change bit 4 in the SIM_GPS register to select the desired

peripheral function.

To deactivate the internal pull-up resistor, clear bit 0 in the

GPIOD_PUR register.

Table 2-2 Signal and Package Information for the 144-Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

56F8366 Datasheet(PDF) 25 Page - Freescale Semiconductor, Inc

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