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56F8366 Datasheet(PDF) 156 Page - Freescale Semiconductor, Inc |
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56F8366 Datasheet(HTML) 156 Page - Freescale Semiconductor, Inc |
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156 / 182 page ![]() 56F8366 Technical Data, Rev. 7 156 Freescale Semiconductor Preliminary 10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing Valid Data Out Set Up Time to WR Deasserted tDOS -0.563 0.25 + DCAOE WWS,WWSS ns -8.315 0.50 Valid Address after WR Deasserted tWAC -3.432 0.25 + DCAEO WWSH ns RD Deasserted to Address Invalid tRDA -1.780 0.00 RWSH ns Address Valid to RD Deasserted tARDD -2.120 1.00 RWSS,RWS ns Valid Input Data Hold after RD Deasserted tDRD 0.00 N/A1 — ns RD Assertion Width tRD 0.279 1.00 RWS ns Address Valid to Input Data Valid tAD -15.723 1.00 RWSS,RWS ns -20.642 1.25 + DCAOE Address Valid to RD Asserted tARDA -2.603 0.00 RWSS ns RD Asserted to Input Data Valid tRDD -13.120 1.00 RWSS,RWS ns -18.039 1.25 + DCAOE WR Deasserted to RD Asserted tWRRD -2.135 0.25 + DCAEO WWSH,RWSS ns RD Deasserted to RD Asserted tRDRD -0.4832 0.00 RWSS,RWSH MDAR3, 4 ns WR Deasserted to WR Asserted tWRWR WWS=0 -1.608 0.75 + DCAEO WWSS, WWSH ns WWS>0 -0.918 1.00 RD Deasserted to WR Asserted tRDWR WWS=0 -0.096 0.50 RWSH, WWSS, MDAR3 ns WWS>0 0.084 0.75 + DCAOE 1. N/A, since device captures data before it deasserts RD 2. If RWSS = RWSH = 0, and the chip select does not change, then RD does not deassert during back-to-back reads. 3. Substitute BMDAR for MDAR if there is no chip select 4. MDAR is active in this calculation only when the chip select changes. Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2 Characteristic Symbol Typical Min Typical Max Unit See Figure RESET Assertion to Address, Data and Control Signals High Impedance tRAZ —21 ns 10-6 Minimum RESET Assertion Duration tRA 16T — ns 10-6 Table 10-16 External Memory Interface Timing (Continued) Characteristic Symbol Wait States Configuration DM Wait States Controls Unit |
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