TRF2443IPFP datasheet(59/72 Pages) TI

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APPLICATION INFORMATION

POWER SUPPLY RAMP-UP PROCEDURE

TRF2443 SPI INITIALIZATION SEQUENCE

EEPROM

Initialize RX PLL (SPI-2)

Initialize TX PLL (SPI-1)

Initialize RX and TX

TRF2443

www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009

In order to assure the correct functionality of the TRF2443 internal registers, it is important to ramp up the

VCCREF power supply at the same time as or before VCCSPI. If VCCREF is powered before VCCSPI, the

EEPROM contents could potentially be erased.

In order to ensure proper operation of the TRF2443, it is important to program the IC through the SPI in a

particular manner. How to do this is the scope of this section. The chip initialization can be broken down into four

parts:

• Acquire information from EEPROM needed for subsequent initializations

• Initialize receiver PLL (SPI-2)

• Initialize transmitter PLL (SPI-1)

• Initialize receiver and transmitter (SPI-3)

There is information stored in the EEPROM that is available to the user to program the TRF2443 into an optimal

state. If desired, the user must first read this information from the EEPROM and make it available for subsequent

SPI programming. See the application note (SLWU064) on how to access EEPROM information.

Write registers 4, 5, 1, and 2 of SPI-2 in this order. Register 2 is the last register to be written because register 2

starts the RX VCO calibration and PLL lock. The time required for this calibration to complete is 12 cycles of the

calibration frequency. The calibration frequency is the external reference frequency divided by the RX_CAL

CLK<2,0> (SPI-2, register 2, B<29,27>) setting. With a 20-MHz external reference and RX_CAL CLK<2,0> =

<111> corresponding to a divider ratio of 16,684, this calibration frequency is 1.2 kHz. Therefore, the calibration

requires 10 ms. The user should set the external reference frequency and the RX_CAL CLK<2,0> setting to

ensure that the calibration frequency does not exceed 800 kHz. Subsequent register writes to SPI-1 and SPI-3

do not affect the RX VCO calibration and can begin immediately on the next SPI clock cycle.

Write registers 4, 5, 1, and 2 of SPI-1 in this order. Register 2 is the last register to be written because register 2

starts the TX VCO calibration and PLL lock. The time required for this calibration to complete is 11 cycles of the

calibration frequency. The calibration frequency is the external reference frequency divided by the TX_CAL

CLK<2,0> (SPI-1, register 2, B<29,27>) setting. With a 20-MHz external reference and TX_CAL CLK<2,0> =

<111>, corresponding to a divider ratio of 16,684, this calibration frequency is 1.2 kHz. Therefore, this calibration

requires 9.2 ms. The user should set the external reference frequency and the TX_CAL CLK<2,0> setting to

ensure that the calibration frequency does not exceed 800 kHz. Subsequent register writes to SPI-3 do not affect

the TX VCO calibration and can begin immediately on the next SPI clock cycle.

Write registers 6, 3, 7, 4, 2, 5, 1, and 1 again of SPI-3 in this order. Register 5 starts the RX dc offset calibration.

does not affect the RX dc-offset calibration. Register 1 is written last because it contains the PWD_TX bit (SPI-3,

is enabled. However, the power alarm circuitry (See the Power Alarm Detector section) is reset from register 1 by

DET_RESET (SPI-3, register 1, B<20>). Because the TX is enabled at the same time the power alarm circuitry is

reset, there exists a race condition which could cause the power alarm to be in either state. To ensure that the

power alarm is properly armed, the DET_RESET (SPI-3, register 1, B<20>) bit should be resent after the

transmitter has been enabled. To do this, register 1 is written a second time.

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