ICS843SDN

FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR

IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR

6

ICS843SDNAG REV. A FEBRUARY 19, 2009

Application Information

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter

performance, power supply isolation is required. The ICS843SDN

provides separate power supplies to isolate any high switching

be individually connected to the power supply plane through vias,

and 0.01µF bypass capacitors should be used for each pin. Figure

requires that an additional 10

Ω resistor along with a 10µF bypass

Figure 1. Power Supply Filtering

Crystal Input Interface

The ICS843SDN has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in

Figure 2 below were determined using a 25MHz, 18pF parallel

resonant crystal and were chosen to minimize the ppm error. The

optimum C1 and C2 values can be slightly adjusted for different

board layouts.

Figure 2. Crystal Input Interface

3.3V

10

Ω

10µF

.01µF

.01µF

XTAL_IN

XTAL_OUT

X1

18pF Parallel Crystal

C1

27p

C2

27p