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TLE7263E Datasheet(PDF) 49 Page - Infineon Technologies AG |
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TLE7263E Datasheet(HTML) 49 Page - Infineon Technologies AG |
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49 / 63 page ![]() TLE 7263E Electrical Characteristics Data Sheet 49 Rev. 1.51, 2007-06-22 CLK setup time t lag 250 – – ns – Clock low after CSN high t beh 125 – – ns – DI setup time t DISU 50 – – ns – DI hold time t DIHO 50 – – ns – Input signal rise time at pin DI, CLK and CSN t rIN – – 50 ns – Input signal fall time at pin DI, CLK and CSN t fIN – – 50 ns – Delay time for mode change from Normal Mode to Sleep Mode t fIN –– 10 µs– CSN high time t CSN(high) 15 – – µs two oscillator periods Data Output Timing Not subject to production test. Specified by design DO rise time t rDO –30 80 ns C L = 100 pF DO fall time t fDO –30 80 ns C L = 100 pF DO enable time t ENDO – – 50 ns low impedance DO disable time t DISDO – – 50 ns high impedance Thermal Prewarning and Shutdown (junction temperatures) (Not subject to production test. Specified by design) V CC1 thermal prewarning ON temperature T jPW 120 145 170 °C bit 0 of SPI diagnosis word V CC1 thermal prewarning hyst. ∆T –25 – K – V CC1/2 thermal shutdown temp. T jSD 155 185 200 °C hysteresis 35 K (typ.) V CC1 ratio of SD to PW temp. T jSD/ T jPW –1.20 – – – Table 13 Electrical Characteristics (cont’d) V S = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Unit Test Condition Min. Typ. Max. |
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