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ICS1893 Datasheet(PDF) 137 Page - Integrated Circuit Systems |
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ICS1893 Datasheet(HTML) 137 Page - Integrated Circuit Systems |
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137 / 152 page  Chapter 10 DC and AC Operating Conditions ICS1893 Rev C 6/6/00 June, 2000 137 ICS1893 - Release Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 10.5.11 10M Media Independent Interface: Transmit Latency Table 10-18 lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • TXD (that is, TXD[3:0]) • TP_TX (that is, TP_TXP and TP_TXN) Figure 10-12 shows the timing diagram for the time periods. Figure 10-12. 10M MII Transmit Latency Timing Diagram Table 10-18. 10M MII Transmit Latency Timing Time Period Parameter Conditions Min. Typ. Max. Units t1 TXD Sampled to MDI Output of First Bit 10M MII – 1.2 2 Bit times TXCLK TXEN TXD † Manchester encoding is not shown. 5 5 5 t1 TP_TX† |
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