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ICS1893 Datasheet(PDF) 141 Page - Integrated Circuit Systems |
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ICS1893 Datasheet(HTML) 141 Page - Integrated Circuit Systems |
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141 / 152 page  Chapter 10 DC and AC Operating Conditions ICS1893 Rev C 6/6/00 June, 2000 141 ICS1893 - Release Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 10.5.15 100M MII / 100M Stream Interface: Receive Latency Table 10-22 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The time periods consist of timings of signals on the following pins: • TP_RX (that is, TP_RXP and TP_RXN) • RXCLK • RXD (that is, RXD[3:0]) Figure 10-16 shows the timing diagram for the time periods. Figure 10-16. 100M MII / 100M Stream Interface: Receive Latency Timing Diagram Table 10-22. 100M MII / 100M Stream Interface Receive Latency Timing Time Period Parameter Conditions Min. Typ. Max. Units t1 First Bit of /J/ into TP_RX to /J/ on RXD 100M MII – 16 17 Bit times t2 First Bit of /J/ into TP_RX to /J/ on RXD 100M Stream Interface – 8 9 Bit times RXCLK TP_RX† † Shown unscrambled. RXD t1 t2 |
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