MX844

5

08/25/06

Drawing No. 084423

www.claremicronix.com

IXYS

MX844

Analog/Digital Converter

Selection of the input channel and the full scale range is accomplished by writing 5 bits in the control

register. An additional 3 bits in the control register in combination with the M1 pin setup the internal clock

dividers. The ADC is a bipolar-input dual slope type with clock period tAD equal to a multiple of the clock

period at pin X1 (tClock). The ADC conversion time consists of 1024 * tAD of auto-zero, 1024 * tAD of

input integration, and 2048 * tAD of reference integration. The result of the analog to digital conversion

can be read using the serial I/O port and is also transmitted on pin AOUT in an asynchronous serial

format. The DRDY pin transitions low at the end of the reference integration period to indicate that data is

stable and may be read through the synchronous serial I/O. The data becomes not valid when DRDY

returns high. The status of DRDY is also available in bit 7 of the ADC_1 register.

The SYNC pin is connected to GND to enable free-running ADC conversions. Alternatively, if SYNC

transitions high, the ADC is immediately driven to the start of the auto-zero time. When SYNC is returned

to a logic low, the next rising edge at pin X2 will start the ADC timing.

The input channel and full scale range may be changed in between ADC conversions, however it is

recommended that such commands be written into the MX844 as soon as possible after pin DRDY

transitions low. This allows the maximum settling time prior to the next ADC conversion.

1023 1024

2047 2048

4095 0

1023 1024

2047 2048

auto-zero

input integrate

reference integrate

next auto-zero

SYNC

AOUT

6 data bits

6 data bits

DRDY and CMP cleared if ADC_2 register is read

CMP is the digital compare output that is described later. AOUT is the asynchronous serial output of the

ADC.

The ADC output code is offset-binary. An example of the coding is shown here for the +/-50mV range and

the corresponding unipolar range of 0 to 100mV:

Bipolar input

Unipolar input

Binary Output (D11:D0)

Hexadecimal

50mV

100mV

111111111111

FFF

0 + 1/2 LSB

50mV + 1/2 LSB

100000000000

800

0 - 1/2 LSB

50mV - 1/2 LSB

011111111111

7FF

-50mV

0

000000000000

000

Two external components, Rin and Cint, should be chosen such that the value of Cint in pF is 4 to 7 * tAD

and the time constant of Rint * Cint is 300 to 450 * tAD. The value of Rint should be between 47K and

220K ohm. For example, for t(AD) = 1.6 uS, a set of suitable values would be 56K ohm and 10nF (RC =

560uS, ratio = 350). The value of the auto-zero capacitor Caz is typically equal to Cint.

VTRIM is either a no-connect pin or can be used to fine

VCC

trim the ADC full scale by +/- 1%. The following circuit

is recommended if fine trimming is desired:

20K

1K

VTRIM

GND